公开(公告)号：JP2009252818A

公开(公告)日：2009-10-29

申请号：JP2008095881

申请日：2008-04-02

申请人： Renesas Technology Corp ,  株式会社ルネサステクノロジ

发明人： TANAKA TOSHIHIKO

IPC分类号： H01L21/027 ,  G01N21/956 ,  G03F1/22 ,  G03F1/24 ,  G03F1/70 ,  G03F1/84

摘要： PROBLEM TO BE SOLVED: To provide a reflective mask capable of mask inspection by pattern comparison on a layout in a mode of scan exposure by injecting exposure light slantly to the mask, and its inspection method.
SOLUTION: The reflective mask for irradiating the exposure light slightly incident to a mask surface over a predetermined exposure area and projecting light reflected on the mask surface to a wafer for scan exposure includes a plurality of rectangular chip regions 11a-11f containing the same mask patterns arranged in a scanning direction 12. When shape correction is made depending on a distance from the center line of an exposure area 21 (azimuth angle θ), the two chip regions 11a and 11b have the identical mask patterns after the shape correction. Thus the identical patterns can be compared with each other on the layout to perform die-to-die inspection for defect inspection of the mask pattern.
COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 要解决的问题：提供一种能够通过模式比较对通过将掩模光倾斜地注入到掩模中的扫描曝光模式中的布局进行掩模检查的反射掩模及其检查方法。 解决方案：用于将预定曝光区域稍微入射到掩模表面的曝光光照射并将在掩模表面上反射的光投影到用于扫描曝光的晶片的反射掩模包括多个矩形芯片区域11a-11f，其包含 在扫描方向12上布置的相同的掩模图案。当根据与曝光区域21的中心线（方位角θ）的距离进行形状校正时，两个芯片区域11a和11b在形状校正之后具有相同的掩模图案 。 因此，可以在布局上将相同的图案彼此进行比较，以对掩模图案的缺陷检查执行管芯到管芯检查。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009251412A

公开(公告)日：2009-10-29

申请号：JP2008101079

申请日：2008-04-09

申请人： Renesas Technology Corp ,  株式会社ルネサステクノロジ

发明人： TERASAWA TSUNEO ,  TANAKA TOSHIHIKO

IPC分类号： G03F1/24 ,  G03F1/84 ,  H01L21/027

摘要： PROBLEM TO BE SOLVED: To provide a device and a method for inspecting mask blank, that improve detection sensitivity to and detection reliability of a phase defect and an amplitude defect which are too high in defect height to detect only through dark field detection. SOLUTION: The device for inspecting mask blank includes a stage 2 on which a reflection type mask blank MB is mounted, a light source 1 which emits inspection light BM, a mirror 10 as a lighting optical system, an imaging optical system L, a two-dimensional array sensor S, a defect detection signal storage unit 6, a defect detection processing unit 7, a defect information storage unit 8, a main control unit 9 which controls the whole device, etc. The stage 2 is provided with a tilting mechanism to vary the angle of incidence and the angle of regular reflection of the inspection light BM on the mask blank MB. COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 要解决的问题：提供一种用于检查掩模毛坯的装置和方法，其提高缺陷高度的过高的相缺陷和振幅缺陷的检测灵敏度和检测可靠性，以仅通过暗场检测来检测 。 解决方案：用于检查掩模坯料的装置包括其上安装有反射型掩模坯料MB的载物台2，发射检查光BM的光源1，作为照明光学系统的反射镜10，成像光学系统L ，二维阵列传感器S，缺陷检测信号存储单元6，缺陷检测处理单元7，缺陷信息存储单元8，控制整个设备的主控制单元等。阶段2设置有 倾斜机构，用于改变掩模坯料MB上的检查光BM的入射角和正常反射角。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009170839A

公开(公告)日：2009-07-30

申请号：JP2008010306

申请日：2008-01-21

申请人： Renesas Technology Corp ,  株式会社ルネサステクノロジ

发明人： TANAKA TOSHIHIKO

IPC分类号： H01L21/027 ,  G03F1/22 ,  G03F1/24 ,  G03F1/36

摘要： PROBLEM TO BE SOLVED: To provide a method for forming mask pattern data for easily and quickly executing mask data processing for flare compensation without losing pattern dimension precision, and to provide a method for manufacturing a semiconductor apparatus.
SOLUTION: A pattern to be corrected is a gate pattern including a wiring section and an active gate section formed on a diffusion layer. The method for forming a mask pattern data includes: extracting a diffusion pattern from design mask pattern data; widening the width of the extracted diffusion layer pattern only by predetermined width Δw to generate a second diffusion layer pattern; extracting a gate pattern existing on the second diffusion layer pattern to generate an extended second active gate section; and performing uniform quantity correction to individual second active gate section.
COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：提供一种用于形成掩模图案数据的方法，用于在不损失图案尺寸精度的情况下容易且快速地执行用于火炬补偿的掩模数据处理，并提供一种制造半导体装置的方法。 解决方案：要校正的图案是包括形成在扩散层上的布线部分和有源栅极部分的栅极图案。 用于形成掩模图案数据的方法包括：从设计掩模图案数据提取扩散图案; 将所提取的扩散层图案的宽度仅扩大预定宽度Δw以产生第二扩散层图案; 提取存在于第二扩散层图案上的栅极图案以产生延伸的第二有源栅极部分; 对各个第二有源栅极部进行均匀的量化校正。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009141223A

公开(公告)日：2009-06-25

申请号：JP2007317695

申请日：2007-12-07

申请人： Renesas Technology Corp ,  Toshiba Corp ,  株式会社ルネサステクノロジ ,  株式会社東芝

发明人： KAMO TAKASHI ,  SUGA OSAMU ,  TANAKA TOSHIHIKO

IPC分类号： H01L21/027 ,  G03F1/22 ,  G03F1/24 ,  G03F7/20

CPC分类号： G03F1/24 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/58

摘要： PROBLEM TO BE SOLVED: To provide a reflective mask capable of suppressing a leak of exposure light from an overlap portion between adjacent shots and reducing an influence of shadowing of the exposure light. SOLUTION: The reflective mask is a reflective mask having a main surface irradiated with the exposure light 40, and has a pattern region 10 provided in the main surface, the pattern region 10 including a multilayered reflective film 2 which reflects the exposure light 40, and first absorber patterns 4 and 5 provided on the multilayered reflective film 2, absorbing the exposure light 40, and having a pattern corresponding to a pattern to be formed on a wafer, and a light shield region 11 provided in the main surface, the light shield region 11 being provided with second absorber patterns 4 to 6 having lower reflectivity to the exposure light 40 than the first absorber patterns 4 and 5 so as to prevent a region of the wafer other than a predetermined region from being irradiated with the exposure light 40 when the pattern is transferred to the predetermined region on the wafer by irradiating the main surface with the exposure light 40. COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：提供一种能够抑制来自相邻镜头之间的重叠部分的曝光光的泄漏并且减少曝光光的阴影影响的反射掩模。 解决方案：反射掩模是具有用曝光光40照射的主表面的反射掩模，并且具有设置在主表面中的图案区域10，图案区域10包括反射曝光光的多层反射膜2 40，以及设置在多层反射膜2上的第一吸收体图案4和5，吸收曝光光40，并且具有与形成在晶片上的图案对应的图案，以及设置在主表面上的遮光区域11， 遮光区域11设置有比第一吸收体图案4和5更低的对曝光光40的反射率的第二吸收体图案4至6，以防止除了预定区域之外的晶片的区域被曝光 当通过用曝光灯40照射主表面将图案转印到晶片上的预定区域时的光40。（C）2009，JPO＆INPIT

公开(公告)号：JP2006156657A

公开(公告)日：2006-06-15

申请号：JP2004344323

申请日：2004-11-29

申请人： Renesas Technology Corp ,  株式会社ルネサステクノロジ

发明人： TANAKA TOSHIHIKO ,  YONEKURA KAZUMASA

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

摘要： PROBLEM TO BE SOLVED: To form wiring patterns with a narrow pitch and to provide a plug connected to the wiring patterns with high tolerance.
SOLUTION: A first pattern 11 is formed on a conductive film and thinned through trim etching. A second pattern 12 of closed loop is formed around a fine first pattern 11a in a self-aligned manner. The second pattern 12 is partially divided into a third pattern 12a. The conductive film is subjected to etching using the third pattern 12a as a mask for the formation of a wiring pattern 13. The wiring pattern 13 is covered with an interlayer insulating film, and then an opening 14 is provided inside the interlayer insulating film so as to make the curved end of the wiring pattern 13 exposed. The opening 14 is filled up with a conductive film for the formation of the plug.
COPYRIGHT: (C)2006,JPO&NCIPI

摘要翻译： 要解决的问题：形成具有窄间距的布线图案，并提供与具有高公差的布线图形连接的插头。 解决方案：第一图案11形成在导电膜上并通过修整蚀刻变薄。 以自对准的方式围绕精细的第一图案11a形成闭环的第二图案12。 第二图案12被部分地分成第三图案12a。 使用第三图案12a作为形成布线图案13的掩模来对导电膜进行蚀刻。布线图案13被层间绝缘膜覆盖，然后在层间绝缘膜内部设置开口14，以便 使布线图案13的弯曲端部露出。 开口14填充有用于形成插头的导电膜。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2010062244A

公开(公告)日：2010-03-18

申请号：JP2008224593

申请日：2008-09-02

申请人： Renesas Technology Corp ,  株式会社ルネサステクノロジ

发明人： IRIKITA NOBUYUKI ,  TANAKA TOSHIHIKO

IPC分类号： H01L21/027 ,  G03F1/22 ,  G03F1/24 ,  G03F1/84 ,  G03F7/20

摘要： PROBLEM TO BE SOLVED: To increase the efficiency of producing semiconductor devices by using an extreme ultra violet (EUV) lithography technique. SOLUTION: In an EUV lithography mask (a reflection type mask) for hole pattern formation including at least an absorber pattern, a multilayer film and a substrate as constituent elements, an absorber of the mask is formed to have such a film thickness that a reduction in exposure margin due to an undesired absorber residue (a black defect) in a hole part on the mask is the same as that in exposure margin due to an absorber missing part (a white defect) of the same area. COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 要解决的问题：通过使用极紫外（EUV）光刻技术来提高半导体器件的制造效率。 解决方案：在用于孔图案形成的EUV光刻掩模（反射型掩模）中，至少包括吸收体图案，多层膜和基板作为构成元件，掩模的吸收体形成为具有这样的膜厚度 由于掩模上的孔部分中的不期望的吸收体残留（黑色缺陷）导致的曝光余量的减少与由于相同面积的吸收体缺失部分（白色缺陷）引起的曝光余量相同。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009092407A

公开(公告)日：2009-04-30

申请号：JP2007260796

申请日：2007-10-04

申请人： Renesas Technology Corp ,  株式会社ルネサステクノロジ

发明人： TERASAWA TSUNEO ,  TANAKA TOSHIHIKO ,  AOTA TATSUYA

IPC分类号： G01N21/956 ,  G03F1/22 ,  G03F1/24 ,  H01L21/027

CPC分类号： G03F1/84 ,  G01N21/47 ,  G01N21/956 ,  G01N2021/4711 ,  G01N2021/95676

摘要： PROBLEM TO BE SOLVED: To provide a mask blank inspection device and method capable of inspecting accurately and simply existence and the kind of a defect of a reflective mask blank.
SOLUTION: The mask blank inspection device is constituted of a stage 2 for mounting a reflective mask blank M thereon, a light source 1 for generating inspection light BM, a mirror 10 serving as an illuminating optical system, a dark field imaging optical system L, a beam splitter BS, two two-dimensional array sensors Sa, Sb, signal storage units 6, 7, an image processing unit 8, and a main control unit 9 for controlling operation of the whole device, or the like. The sensor Sa is arranged on a position displaced by a predetermined distance d1 along a light traveling direction from an imaging plane IPa of a light flux 14a. The sensor Sb is arranged on a position displaced by a predetermined distance d2 in the opposite direction to the light traveling direction from an imaging plane IPb of a light flux 14b.
COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：提供一种能够准确，简单地存在和检查反光掩模坯的缺陷的种类的掩模毛坯检查装置和方法。 解决方案：掩模毛坯检查装置由用于安装反射掩模毛坯M的载物台2，用于产生检查光BM的光源1，用作照明光学系统的反射镜10，暗视野成像光学 系统L，分束器BS，两个二维阵列传感器Sa，Sb，信号存储单元6,7，图像处理单元8和用于控制整个设备的操作的主控制单元9等。 传感器Sa配置在从光通量14a的摄像面IPa沿着光行进方向偏移预定距离d1的位置上。 传感器Sb布置在从光通量14b的成像平面IPb沿与光行进方向相反的方向偏移预定距离d2的位置处。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007086587A

公开(公告)日：2007-04-05

申请号：JP2005277332

申请日：2005-09-26

申请人： National Institute Of Advanced Industrial & Technology ,  Renesas Technology Corp ,  株式会社ルネサステクノロジ ,  独立行政法人産業技術総合研究所

发明人： TANAKA TOSHIHIKO ,  SUGA OSAMU ,  TERASAWA TSUNEO ,  HIGUCHI TETSUYA ,  SAKANASHI HIDENORI ,  NOZATO HIROKAZU ,  MATSUNAWA TETSUAKI

IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50

CPC分类号： G03F1/36

摘要： PROBLEM TO BE SOLVED: To provide mask designing techniques capable of shortening the increased OPC (Optical Proximity Correction) processing time, shortening the manufacture TAT (Turn Around Time) of a semiconductor device, thereby reducing cost. SOLUTION: A cell library pattern constituting a basic configuration of a semiconductor circuit pattern is preliminarily subjected to an OPC processing for the layout of a single pattern, and the processed cell library pattern is used to produce a semiconductor chip. A plurality of cell libraries are laid to design a mask pattern and the correction amount by the OPC applied to the cell library is changed by considering the influences of cell library patterns laid in the periphery. Further, a group of cells in the identical layout of the objective cell as well as peripheral cells is extracted and registered as a cell set, so that OPC on identical cell sets is carried out not by repeating computation but by copying. COPYRIGHT: (C)2007,JPO&INPIT

摘要翻译： 要解决的问题：提供能够缩短增加的OPC（光学邻近校正）处理时间的掩模设计技术，缩短半导体器件的制造TAT（周转时间），从而降低成本。 解决方案：构成半导体电路图案的基本配置的单元库图案预先进行用于单一图案布局的OPC处理，并且处理的单元库图案用于制造半导体芯片。 设置多个单元库以设计掩模图案，并且通过考虑周边设置的单元库图案的影响来改变通过应用于单元库的OPC的校正量。 此外，提取了目标单元以及外围单元的相同布局的一组单元，并将其注册为单元组，使得不是通过重复计算而是通过复制来执行相同单元组上的OPC。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005242004A

公开(公告)日：2005-09-08

申请号：JP2004052047

申请日：2004-02-26

申请人： Renesas Technology Corp ,  株式会社ルネサステクノロジ

发明人： TANAKA TOSHIHIKO

IPC分类号： G03F1/36 ,  G03F1/70 ,  G03F7/20 ,  H01L21/027 ,  G03F1/08

CPC分类号： G03F7/70425 ,  G03F7/70441

摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device and a method for preparing mask pattern data by which a pattern shape to be formed on a wafer can be stabilized.
SOLUTION: The method for manufacturing the semiconductor device, which has a first wiring pattern extending in the longitudinal direction and a second pattern having the same shape as the first wiring pattern and extending in the direction (transverse direction) orthogonal to the longitudinal direction, comprises: a step of exposing along a mask pattern which contains a mask pattern 16 for forming the first pattern and a mask pattern 17 for forming the second pattern by using illumination with linearly polarized light; and a step of forming the first and second patterns following the mask patterns 16, 17 after exposure, wherein shapes of the mask patterns 17, 17 are different from each other.
COPYRIGHT: (C)2005,JPO&NCIPI

摘要翻译： 要解决的问题：提供一种用于制造半导体器件的方法和用于制备可以稳定在晶片上形成的图案形状的掩模图案数据的方法。 解决方案：制造半导体器件的方法，该半导体器件具有沿纵向方向延伸的第一布线图形和第二图案，其形状与第一布线图形相同，并且在垂直于纵向的方向（横向）上延伸 方向包括：沿着包含用于形成第一图案的掩模图案16的掩模图案曝光的步骤和用于通过使用具有线性偏振光的照明形成第二图案的掩模图案17; 以及在曝光之后，在掩模图案16,17之后形成第一和第二图案的步骤，其中掩模图案17,17的形状彼此不同。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004004299A

公开(公告)日：2004-01-08

申请号：JP2002159776

申请日：2002-05-31

申请人： Renesas Technology Corp ,  株式会社ルネサステクノロジ

发明人： ODAKA TAKAHIRO ,  TANAKA TOSHIHIKO ,  HATTORI KOJI ,  FUKUDA HIROSHI

IPC分类号： G03F7/004 ,  G03F1/32 ,  G03F1/56 ,  G03F7/20 ,  G03F7/40 ,  H01L21/027 ,  H01L21/28 ,  H01L21/302 ,  H01L21/31 ,  H01L21/339 ,  H01L21/44 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  G03F1/08

CPC分类号： G03F1/32 ,  G03F1/56 ,  G03F7/405 ,  H01L21/76802 ,  Y10S438/942 ,  Y10S438/945 ,  Y10S438/947 ,  Y10S438/948 ,  Y10S438/949

摘要： PROBLEM TO BE SOLVED: To always acquire high dimensional accuracy with little variation in exposure throughput (number of sheets) by preventing the deformation of a resist mask using resist as a light shielding body due to irradiation with exposure light.
SOLUTION: Photomask patterns are formed by using a resist containing Si in a base resin or a resist having with metals, such as Si, introduced by a silylation process as the light shielding body, thereby improving the resistance to active oxygen.
COPYRIGHT: (C)2004,JPO