公开(公告)号：JP2015032969A

公开(公告)日：2015-02-16

申请号：JP2013160916

申请日：2013-08-02

Applicant: Tdk株式会社 ,  Tdk Corp ,  Tdk株式会社

Inventor： TOMAKI SHIGEMITSU ,  KAWADA TOMOAKI ,  HATANAKA KIYOSHI ,  SAKURAI TOSHIO ,  KOSAKA YASUNORI

IPC: H01P3/16 ,  H01P1/20

CPC classification number: H01P1/2002 ,  H01P3/16 ,  H01P7/10

Abstract: 【課題】1GHz〜10GHzの範囲内の1つ以上の周波数の電磁波を伝搬させる誘電体線路を実現する。【解決手段】誘電体線路2は、第1の比誘電率を有する第1の誘電体よりなる線路部10と、第2の比誘電率を有する第2の誘電体よりなる周囲誘電体部20とを備えている。線路部10は、1GHz〜10GHzの範囲内の1つ以上の周波数の電磁波を伝搬させる。周囲誘電体部20は、線路部10における電磁波の伝搬方向に直交する断面において、線路部10の周囲に存在する。第1の比誘電率は、1000以上である。第2の比誘電率は、第1の比誘電率よりも小さい。【選択図】図1

Abstract translation: 要解决的问题：实现用于传播1-10GHz范围内的一个或多个频率的电磁波的介质线。解决方案：介质线2包括由具有第一相对介电常数的第一电介质组成的线10和 由具有第二相对介电常数的第二电介质组成的外围电介质20。 线10在1-10GHz的范围内传播一个或多个频率的电磁波。 外围电介质20在线10的与电磁波的传播方向正交的横截面中存在于线10周围。 第一相对介电常数为1000以上。 第二相对介电常数小于第二相对介电常数。

公开(公告)号：JP2013219019A

公开(公告)日：2013-10-24

申请号：JP2013034612

申请日：2013-02-25

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： HATANAKA KIYOSHI ,  SUZUKI SHINGO ,  ASAKURA KENSAKU ,  FUJIMORI TAKAHIRO

IPC: H01T4/12 ,  H01C7/12 ,  H01T4/10 ,  H05F3/04

CPC classification number: H01T1/20 ,  H01T4/12

Abstract: PROBLEM TO BE SOLVED: To provide a static-electricity countermeasure element causing no separation of a discharge electrode, suppressed in an initial short-circuit fault, less in variation of peak voltage, and further excellent in productivity.SOLUTION: A static-electricity countermeasure element 100 includes: an insulating laminated body 11; discharge electrodes 12, 13 arranged facing each other while separated from each other, in the insulating laminated body 11; and a discharge inducing section 14 disposed in the vicinity of an area including a region between the discharge electrodes 12, 13. In the static-electricity countermeasure element 100, a material that is not sintered at the temperature at which the insulating laminated body 11 is fired is used as an insulating inorganic material in the discharge inducing section.

Abstract translation: 要解决的问题：提供一种不会分离放电电极的静电对策元件，抑制初始短路故障，峰值电压变化小，生产性更好。解决方案：静电对策 元件100包括：绝缘层叠体11; 绝缘层叠体11中彼此分离相对排列的放电电极12,13; 以及设置在包括放电电极12,13之间的区域的区域附近的放电诱导部分14.在静电对抗元件100中，在绝缘层叠体11的温度下不被烧结的材料 在放电诱导部中用作绝缘无机材料。

公开(公告)号：JP2011211158A

公开(公告)日：2011-10-20

申请号：JP2010267646

申请日：2010-11-30

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： SAKURAI TOSHIO ,  KOSARA HISASHI ,  ARASHI TOMOHIRO ,  HATANAKA KIYOSHI ,  MIYAUCHI TAIJI

IPC: H01G4/33

CPC classification number: H01G4/1227 ,  B32B18/00 ,  C04B35/20 ,  C04B35/462 ,  C04B35/6263 ,  C04B35/62675 ,  C04B35/62685 ,  C04B2235/3208 ,  C04B2235/3215 ,  C04B2235/3224 ,  C04B2235/3234 ,  C04B2235/3262 ,  C04B2235/3275 ,  C04B2235/3281 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/3409 ,  C04B2235/3445 ,  C04B2235/36 ,  C04B2235/407 ,  C04B2235/408 ,  C04B2235/6025 ,  C04B2237/341 ,  C04B2237/346 ,  C04B2237/58 ,  C04B2237/60 ,  H01G4/20 ,  H01G4/30 ,  Y10T428/12729 ,  Y10T428/12806

Abstract: PROBLEM TO BE SOLVED: To provide a ceramic electronic component that prevents laminated dielectric layers of different materials from peeling from each other even when the dielectric layers are laminated and formed, and to provide a method of manufacturing the ceramic electronic component.SOLUTION: The ceramic electronic component (10) includes a first dielectric layer (11), a second dielectric layer (12), and a boundary reaction layer (13). The first dielectric layer (11) is a layer containing BaO, NdO, and TiO, the second dielectric layer (12) is a layer containing a material different from the material of the first dielectric layer (11), and the boundary reaction layer (13) is a layer formed between the first dielectric layer (11) and the second dielectric layer (12) and containing at least one of Zn, Ti, Cu, and Mg.

Abstract translation: 要解决的问题：提供一种陶瓷电子部件，其能够防止不同材料的层叠电介质层彼此剥离，即使在层叠和形成介电层的同时，也提供陶瓷电子部件的制造方法。 电子部件（10）包括第一电介质层（11），第二电介质层（12）和边界反应层（13）。 第一电介质层（11）是含有BaO，NdO和TiO的层，第二电介质层（12）是含有与第一介电层（11）的材料不同的材料的层，以及边界反应层 13）是形成在第一电介质层（11）和第二电介质层（12）之间并含有Zn，Ti，Cu和Mg中的至少一种的层。

公开(公告)号：JP2008172029A

公开(公告)日：2008-07-24

申请号：JP2007003908

申请日：2007-01-11

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： HATANAKA KIYOSHI ,  NISHINO HARUO

IPC: H05K3/46 ,  H01L23/12

Abstract: PROBLEM TO BE SOLVED: To facilitate removal of a baked material within a cavity upon manufacture of a multilayer ceramic substrate having the cavity having a small opening dimension. SOLUTION: A method of manufacturing a multilayer ceramic substrate includes steps of: forming a laminate by laminating a plurality of ceramic green sheets 21 including a green sheet 30 for formation of a cavity having a through hole formed therein to be associated with the cavity; laminating a shrinkage suppressing green sheet 22 and an uppermost layer composite green sheet 29 on the outermost layer surface of the laminate; locating a first fitting sheet 25 as a shrinkage suppressing green sheet piece on the bottom surface of the cavity; locating and pressing a burying green sheet 31a and a second fitting sheet 28 on the first fitting sheet 25 in a way they bury the cavity; baking the laminate; and removing a baked material within the cavity after baked. At least part of the burying green sheet 31a and the second fitting sheet 28 has a shrinkage larger than that of the ceramic green sheet 21. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：在制造具有小开口尺寸的空腔的多层陶瓷基板时，为了便于在空腔内去除烘烤材料。 ＆lt; P＆gt;解决方案：制造多层陶瓷基板的方法包括以下步骤：通过层叠多个陶瓷生片21来形成层压体，所述多个陶瓷生片21包括用于形成其中形成有通孔的空腔的生片30， 腔; 在层叠体的最外层表面上层叠收缩抑制生片22和最上层复合生片29。 将第一配合片25定位为在腔的底表面上的收缩抑制生片片; 以埋入空腔的方式将埋藏的生片31a和第二装配片28定位并按压在第一装配片25上; 烘烤层压板; 并烘烤后在腔内去除烘烤的材料。 掩埋生片31a和第二配合片28的至少一部分的收缩率大于陶瓷生片21的收缩率。（C）2008，JPO＆INPIT

公开(公告)号：JP2007317711A

公开(公告)日：2007-12-06

申请号：JP2006142717

申请日：2006-05-23

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： KOSARA HISASHI ,  HATANAKA KIYOSHI ,  NISHINO HARUO ,  UEMATSU HIROYUKI

IPC: H05K3/46 ,  H01L23/12 ,  H01L23/13

Abstract: PROBLEM TO BE SOLVED: To provide a multi-functional laminated substrate which responds to various purposes and demands, and a manufacturing method thereof. SOLUTION: Two kinds of ceramic laminates 2, 3 consisting of mutually different kinds of ceramic materials are integrated with each other with a predetermined gap by a columnar conductor 5 formed of a sintered metal and in an electrically connected state. The gap between the ceramic laminates 2, 3 is filled with resin 4 to form a resin layer 4. The ceramic laminates 2, 3 and the columnar conductor 5 are simultaneously baked. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供一种响应各种目的和要求的多功能层叠基板及其制造方法。 解决方案：由相互不同种类的陶瓷材料组成的两种陶瓷层压体2,3通过由烧结金属形成的电连接状态的柱状导体5以预定间隙彼此一体化。 陶瓷层叠体2,3之间的间隙填充有树脂4以形成树脂层4.同时烘烤陶瓷层压体2,3和柱状导体5。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006269767A

公开(公告)日：2006-10-05

申请号：JP2005086000

申请日：2005-03-24

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： ENDO KENJI ,  HIRAKAWA SHOJI ,  HATANAKA KIYOSHI ,  NISHINO HARUO

IPC: H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a ceramic substrate and a multilayer ceramic substrate capable of efficiently obtaining a large capacity in the case of forming a capacitor or the like for instance, and sufficiently securing dimension accuracy even when the electrode of a large area is installed.
SOLUTION: A ceramic layer constituting the ceramic substrate or the multilayer ceramic substrate is constituted of a ceramic single layer region formed in a prescribed thickness and an electrode layer forming region where an electrode layer and a ceramic layer are laminated. Then, the thickness of the ceramic single layer region and the thickness of the electrode layer forming region are set to be almost equal. To put it concretely, the difference of the thickness between the ceramic single layer region and the electrode forming region is within 10% of the thickness of the ceramic single layer region. Also, the specific inductive capacity of a ceramic material constituting the ceramic layer of the electrode layer forming region is larger than the specific inductive capacity of the ceramic material constituting the ceramic single layer region.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种陶瓷基板和多层陶瓷基板，其能够在形成电容器等的情况下能够有效地获得大容量，并且即使当大的电极也能够充分地确保尺寸精度 区域已安装。 构成陶瓷基板或多层陶瓷基板的陶瓷层由规定厚度形成的陶瓷单层区域和层叠有电极层和陶瓷层的电极层形成区域构成。 然后，将陶瓷单层区域的厚度和电极层形成区域的厚度设定为几乎相等。 具体来说，陶瓷单层区域和电极形成区域之间的厚度差在陶瓷单层区域的厚度的10％以内。 此外，构成电极层形成区域的陶瓷层的陶瓷材料的比感应能力大于构成陶瓷单层区域的陶瓷材料的比感应能力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004265898A

公开(公告)日：2004-09-24

申请号：JP2003012384

申请日：2003-01-21

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： HATANAKA KIYOSHI ,  NINOMIYA HIDEAKI ,  NISHINO HARUO ,  TAKAHASHI TAKESHI

IPC: H05K3/46 ,  H01L23/12 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03

CPC classification number: H05K1/0306 ,  H01L23/15 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0187 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a multilayered ceramic substrate that makes the formation of an element easier by suppressing the thickness of the whole multilayered ceramic substrate to the utmost without exerting bad influences upon the layers constituting the substrate.
SOLUTION: A first unburned substrate 4 is formed by laminating a plurality of first green sheets which constitute first ceramic layers after burning upon another. Then a second unburned substrate is formed by laminating second green sheets which constitute second ceramic layers after burning upon another. Then recessed sections 10 are formed in the first unburned substrate 4. In addition, first unburned blocks 6 are formed from the second unburned substrate so that the blocks 6 may be put in the recessed sections 10, and put in the recessed sections 10 so that the direction of lamination A of the first green sheets may become equal to that A' of the second green sheets. Then the first unburned substrate 4 containing the first unburned blocks 6 in the recessed sections 10 is burned.
COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供通过最大限度地抑制整个多层陶瓷衬底的厚度而使元件形成更容易的多层陶瓷衬底，而不会对构成衬底的层产生不良影响。 解决方案：第一未烧制基板4通过在另一个烧结之后层叠构成第一陶瓷层的多个第一生坯而形成。 然后通过在另一个烧成之后层叠构成第二陶瓷层的第二生片来形成第二未烧基板。 然后，凹部10形成在第一未燃烧基板4上。此外，第一未燃烧块6由第二未燃烧基板形成，使得块6可以放入凹部10中，并放入凹部10中，使得 第一生片的层叠方向A可以变得等于第二生片的A'。 然后，将包含凹部10中的第一未燃烧块6的第一未燃烧基板4燃烧。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2013144631A

公开(公告)日：2013-07-25

申请号：JP2012221187

申请日：2012-10-03

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： MASAOKA RAITARO ,  SAKURAI TOSHIO ,  ARASHI TOMOHIRO ,  CHOI KYUNG-KU ,  HATANAKA KIYOSHI

IPC: C04B35/462 ,  H01B3/12 ,  H01G4/12 ,  H01G4/30

CPC classification number: C04B35/462 ,  C03C14/00 ,  C04B35/20 ,  C04B35/468 ,  C04B35/62685 ,  C04B2235/3215 ,  C04B2235/3224 ,  C04B2235/3234 ,  C04B2235/3236 ,  C04B2235/3284 ,  C04B2235/3409 ,  C04B2235/3445 ,  C04B2235/36 ,  C04B2235/77 ,  H01G4/1227

Abstract: PROBLEM TO BE SOLVED: To provide a dielectric ceramic composition capable of low-temperature sintering and excellent in chemical durability without increasing the addition of minor components.SOLUTION: The dielectric ceramic composition includes a component represented by composition formula {α(xBaO.yNdO.zTiO)+β(2MgO.SiO)} as a main component and zinc oxide, boron oxide, and a glass having a softening point equal to or lower than a certain temperature as minor components with respect to the main component. In the dielectric ceramic composition, x, y, and z that represent molar ratios of BaO, NdO, and TiOrespectively are in certain ranges and α and β that represent volume ratios of subcomponents (xBaO.yNdO.zTiOand 2MgO.SiO) in the main component are in certain ranges. When the minor components are represented by aZnO, bBO, and cglass respectively, a, b, and c that represent mass ratios of the respective minor components to the main component are in certain ranges.

Abstract translation: 要解决的问题：提供一种能够进行低温烧结并且化学耐久性优异的电介质陶瓷组合物，而不增加少量组分的添加。溶解性：介电陶瓷组合物包括由组成式{α（xBaO.yNdO。 zTiO）+＆bgr;（2MgO.SiO）}作为主要成分，氧化锌，氧化硼和软化点等于或低于一定温度的玻璃作为主要成分的次要成分。 在介电陶瓷组合物中，表示BaO，NdO和TiO的摩尔比的x，y和z分别在一定范围内，α和bgr; 表示主要成分中的子成分（xBaO.yNdO.zTiO和2MgO.SiO）的体积比在一定范围内。 当次要组分分别由ZnO，bBO和cglass表示时，表示各个次要组分与主要组分的质量比的a，b和c在一定范围内。

公开(公告)号：JP2008166307A

公开(公告)日：2008-07-17

申请号：JP2006350628

申请日：2006-12-26

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： MIYAUCHI TAIJI ,  SUZUKI TOSHIYUKI ,  HIRAKAWA SHOJI ,  NAKAMURA TOMOKO ,  MIYAKOSHI TOSHINOBU ,  HATANAKA KIYOSHI

IPC: H05K3/46

CPC classification number: H05K3/38 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/017 ,  H05K2203/1163 ,  H05K2203/308 ,  Y10T428/31678 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable multilayer ceramic substrate by ensuring sufficient bonding strength of a surface conductor under initial state and after elapse of time (e.g., after PCT). SOLUTION: The multilayer ceramic substrate 1 has a surface conductor 5 at least on one surface of a laminate 2 consisting of a plurality of ceramics substrate layers 21-24. A reaction phase formed through reaction of ceramics component in the ceramics substrate layers 21, 24 and glass component in the surface conductor 5 is deposited on the interface of the ceramics substrate layers 21, 24 and the surface conductor 5. For example, ZnAl 2 O 4 is formed as the reaction phase through reaction of alumina filler in the ceramics substrate layer and Zn in the surface conductor. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：通过确保在初始状态下和经过时间之后（例如，在PCT之后）表面导体的足够的结合强度来提供高度可靠的多层陶瓷基板。 解决方案：多层陶瓷基板1在由多个陶瓷基板层21-24组成的层叠体2的至少一个表面上具有表面导体5。 通过陶瓷基体层21,24中的陶瓷成分和表面导体5中的玻璃成分的反应形成的反应相沉积在陶瓷基板层21,24和表面导体5的界面上。例如，ZnAl 4 。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007317712A

公开(公告)日：2007-12-06

申请号：JP2006142718

申请日：2006-05-23

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： KOSARA HISASHI ,  HATANAKA KIYOSHI ,  NISHINO HARUO ,  UEMATSU HIROYUKI

IPC: H05K3/46

Abstract: PROBLEM TO BE SOLVED: To realize further miniaturization by realizing high-density mounting of a chip component, and to ensure low profile and connection reliability. SOLUTION: A composite wiring board is provided with: a ceramic substrate 1; a resin layer 3 formed on at least one surface of the ceramic substrate 1; a conductor layer 6 formed on the surface of the resin layer 3; and a chip component 5 having an electrode formation surface 4a having a bump electrode 5 formed thereon. The chip component 5 is embedded in the resin layer 3 in the state where the electrode formation surface 4a reversely faces the ceramic substrate 1, and is connected to the conductor layer 6 by exposing the bump electrode 5 to the surface of the resin layer 3. A columnar conductor 11 piercing the resin layer 3 in a thickness direction is formed, and the columnar conductor 11 is preferably made of a sintered metal. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：通过实现芯片组件的高密度安装来实现进一步的小型化，并且确保低轮廓和连接可靠性。 ＆lt; P＆gt;解决方案：复合布线板设置有：陶瓷基板1; 形成在陶瓷基板1的至少一个表面上的树脂层3; 形成在树脂层3的表面上的导体层6; 以及具有在其上形成有凸起电极5的电极形成面4a的片状部件5。 在电极形成面4a与陶瓷基板1相反的状态下，将芯片部件5嵌入到树脂层3中，通过将突起电极5暴露在树脂层3的表面，与导体层6连接。 形成在厚度方向上贯通树脂层3的柱状导体11，柱状导体11优选由烧结金属制成。 版权所有（C）2008，JPO＆INPIT