公开(公告)号：JP5371156B2

公开(公告)日：2013-12-18

申请号：JP2011263276

申请日：2011-12-01

Applicant: 株式会社半導体エネルギー研究所

Inventor： 英人 大沼 ,  一郎 上原

IPC: H01L21/336 ,  G02F1/1368 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L21/28114 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/66598 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863 ,  Y10S438/949

Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

公开(公告)号：JP2007242754A

公开(公告)日：2007-09-20

申请号：JP2006060623

申请日：2006-03-07

Applicant: Miyagi Oki Electric Co Ltd ,  Oki Electric Ind Co Ltd ,  宮城沖電気株式会社 ,  沖電気工業株式会社

Inventor： SEO EISUKE

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  H01L29/66598

Abstract: PROBLEM TO BE SOLVED: To provide an LDD (lightly doped drain) semiconductor device which allows less drain currents to flow when in an off state, and which is capable of dealing with high voltage.
SOLUTION: A polysilicon film 4a, a CVD oxide film 5a, and a resist pattern 6 serving as a gate electrode 7 are formed on a thermal oxidation film 3 (step 2). Subsequently, the CVD oxide film 5a is side etched to form a CVD oxide film 5b with a size smaller than the polysilicon film 4a (step 3). A high concentration impurity is injected, using the resist pattern 6 as a mask, to form a high concentration source-drain region 8 at a position where the source-drain region 8 does not overlap the polysilicon film 4a. Then, the resist pattern 6 is removed, and a low concentration impurity is injected, using the CVD oxide film 5b as a mask, to form a low concentration LDD region at a position where the LDD region overlaps the gate electrode 7 made of the polysilicon film 4a.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种LDD（轻掺杂漏极）半导体器件，其在处于断开状态时允许较少的漏极电流流动，并且能够处理高电压。 解决方案：在热氧化膜3上形成多晶硅膜4a，CVD氧化膜5a和用作栅电极7的抗蚀图案（步骤2）。 接着，对CVD氧化膜5a进行侧面蚀刻，形成尺寸小于多晶硅膜4a的CVD氧化膜5b（步骤3）。 使用抗蚀剂图案6作为掩模来注入高浓度杂质，以在源极 - 漏极区域8不与多晶硅膜4a重叠的位置处形成高浓度源极 - 漏极区域8。 然后，除去抗蚀剂图案6，并使用CVD氧化膜5b作为掩模注入低浓度杂质，以在LDD区域与由多晶硅制成的栅电极7重叠的位置处形成低浓度LDD区域 电影4a。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006024834A

公开(公告)日：2006-01-26

申请号：JP2004203057

申请日：2004-07-09

Applicant: Nec Corp ,  日本電気株式会社

Inventor： IGA DAISUKE

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/336

CPC classification number: H01L29/66598 ,  H01L21/268 ,  H01L29/66757 ,  H01L29/78621

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device where any regions other than a doped region suffer thermal damage a little even if the doped region is subjected to an impurity activation treatment by the use of excimer laser annealing, when a thin film transistor equipped with a gate electrode of laminated structure is formed on an insulating transparent board large in area, to provide its manufacturing method, and to provide a display device equipped with the semiconductor device.
SOLUTION: The gate electrode 6 is formed on a polysilicon layer 7 provided on a glass board 1 through a gate insulating layer 3. The doped region 8 is formed in the polysilicon layer 7 by injecting impurities into the polysilicon layer 7 through the gate electrode 6 as a mask, then an insulating layer 4 is formed on the gate electrode 6, and an insulating film 5 is formed so as to cover them. At this point, a stepped part which is set low at the peripheral part of the gate electrode 6 and high at its center is formed on the surface of the insulating film 5 located on the gate electrode 6, and furthermore the parts of the insulating layer 4 and the insulating film 5 located above the center of the gate electrode 6 are set higher in reflectance to a laser beam than the parts of the insulating film 5 and the gate insulating layer 3 above the doped region 8.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种半导体器件，其中除了掺杂区域之外的任何区域，即使通过使用准分子激光退火对掺杂区域进行杂质活化处理也会稍微受到热损伤，当薄膜 配备有层叠结构的栅电极的晶体管形成在大面积的绝缘透明板上，以提供其制造方法，并提供配备有该半导体器件的显示装置。 解决方案：栅极6通过栅极绝缘层3形成在设置在玻璃板1上的多晶硅层7上。掺杂区8通过将杂质注入多晶硅层7中而形成在多晶硅层7中 栅电极6作为掩模，然后在栅电极6上形成绝缘层4，并且形成绝缘膜5以覆盖它们。 此时，在位于栅电极6上的绝缘膜5的表面上形成在栅电极6的周边部分设置为低并且在其中心处高的阶梯部分，此外，绝缘层的部分 并且位于栅电极6的中心之上的绝缘膜5比在掺杂区域8上方的绝缘膜5和栅极绝缘层3的部分对激光束的反射率设定得更高。权利要求（ C）2006，JPO＆NCIPI

公开(公告)号：JP2005197703A

公开(公告)日：2005-07-21

申请号：JP2004376818

申请日：2004-12-27

Applicant: Dongbu Electronics Co Ltd ,  ドンブ エレクトロニクス カンパニー リミテッド

Inventor： KIM DAE-KYEUN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66598 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468

Abstract: PROBLEM TO BE SOLVED: To form an impurity region having an LDD structure, only through a one-time ion implantation step, without forming a gate spacer film.
SOLUTION: The manufacturing method for a MOSFET includes the steps of sequentially forming a gate insulating film and a gate conducting film onto a semiconductor substrate, patterning the gate conducting film to form a first conducting film having a small thickness and a second conducting film having a thickness larger than that of the first gate conducting film, forming an insulating film pattern on a side surface of the second gate conducting film, sequentially eliminating exposed parts of the first gate conducting film and the gate insulating film in an etching step that uses the insulating film pattern as an etching mask, performing an etching step on the insulating film pattern, to also eliminate a gate insulating film on the underside of the first gate conducting film, and carrying out the ion implantation step that makes the first gate conducting film an ion implantation control film for a lightly-doped region, to form a source/drain region composed of a lightly-doped region and a heavily-doped region onto the semiconductor substrate.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：仅通过一次离子注入步骤形成具有LDD结构的杂质区域，而不形成栅极间隔膜。 解决方案：MOSFET的制造方法包括以下步骤：在半导体衬底上依次形成栅极绝缘膜和栅极导电膜，图案化栅极导电膜以形成具有小厚度的第一导电膜和第二导电膜 膜，其厚度大于第一栅极导电膜的厚度，在第二栅极导电膜的侧表面上形成绝缘膜图案，在蚀刻步骤中顺序地消除第一栅极导电膜和栅极绝缘膜的暴露部分， 使用绝缘膜图案作为蚀刻掩模，对绝缘膜图案进行蚀刻步骤，还消除第一栅极导电膜的下侧上的栅极绝缘膜，并且执行使第一栅极导通的离子注入步骤 对用于轻掺杂区域的离子注入控制膜进行成膜，以形成由轻掺杂区域构成的源极/漏极区域 以及在半导体衬底上的重掺杂区域。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP4664557B2

公开(公告)日：2011-04-06

申请号：JP2001522600

申请日：2000-09-06

Applicant: シャープ株式会社

Inventor： 雅行 中野 ,  史善 吉岡 ,  浩 岩田

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/10 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/66598 ,  H01L21/26586 ,  H01L21/28525 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6659

公开(公告)号：JP4649896B2

公开(公告)日：2011-03-16

申请号：JP2004203057

申请日：2004-07-09

Applicant: 日本電気株式会社

Inventor： 大輔 伊賀

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/336

CPC classification number: H01L29/66598 ,  H01L21/268 ,  H01L29/66757 ,  H01L29/78621

公开(公告)号：JP4446949B2

公开(公告)日：2010-04-07

申请号：JP2005280957

申请日：2005-09-27

Applicant: 三星電子株式会社Samsung Electronics Co.,Ltd.

Inventor： 滋 欽 具 ,  東 浩 安 ,  哲 準 崔 ,  載 潤 柳 ,  錫 薫 洪 ,  哲 性 金

IPC: H01L21/28 ,  H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08

CPC classification number: H01L29/66598 ,  H01L21/28518 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66636

公开(公告)号：JP2006066927A

公开(公告)日：2006-03-09

申请号：JP2005280957

申请日：2005-09-27

Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社Samsung Electronics Co.,Ltd.

Inventor： AHN DONG HUL ,  GU JIKIN ,  KIN TETSUSEI ,  RYU SAIJUN ,  KO SHAKKUN ,  SAI TETSUJUN

IPC: H01L21/28 ,  H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/41

CPC classification number: H01L29/66598 ,  H01L21/28518 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66636

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an elevated salicide source/drain region, and a semiconductor element having a T-type element isolation film. SOLUTION: The method for forming the elevated salicide source/drain region 80 has an ion implantation process for forming the source/drain region 80 by adjusting the depth of a wide trench region. The head section of the T-type element isolation film 71 is constituted in the ion implantation process. Conductive imputities are implanted into the lower part 81 of the wide trench region extended to both the sides right and left from the upper end of the narrow trench region. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种形成提高的自对准硅源/漏区的方法以及具有T型元件隔离膜的半导体元件。 解决方案：用于形成升高的自对准硅化物源极/漏极区域80的方法具有用于通过调整宽沟槽区域的深度来形成源极/漏极区域80的离子注入工艺。 T型元件隔离膜71的头部由离子注入工序构成。 将导电插补注入到从窄沟槽区域的上端向右和向左延伸的宽沟槽区域的下部81中。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP6121350B2

公开(公告)日：2017-04-26

申请号：JP2014047168

申请日：2014-03-11

Applicant: マイクロソフト テクノロジー ライセンシング,エルエルシー ,  マイクロソフト テクノロジー ライセンシング,エルエルシー

Inventor： 俊敬 宮田 ,  俊敬 宮田

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/31111 ,  H01L21/28035 ,  H01L21/28052 ,  H01L21/28158 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/7831 ,  H01L29/7833

公开(公告)号：JP4057808B2

公开(公告)日：2008-03-05

申请号：JP2001373316

申请日：2001-12-06

Applicant: 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.

Inventor： 廷 洙 金

IPC: H01L21/8244 ,  H01L21/336 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L29/66598 ,  H01L21/76895 ,  H01L27/1104 ,  H01L29/6653 ,  H01L29/6659