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    ERROR DETECTION FOR SRAM USED IN A SAFETY-CRITICAL DOMAIN
    1.
    发明申请
    ERROR DETECTION FOR SRAM USED IN A SAFETY-CRITICAL DOMAIN 有权

    公开(公告)号：US20250157561A1

    公开(公告)日：2025-05-15

    申请号：US18389056

    申请日：2023-11-13

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Uma Sankara Rao Balla ,  Carl Kittredge Wakeland ,  Kaushal Amolak Sanghai ,  Balatripura S. Chavali ,  Andy Sung

    IPC: G11C29/42

    Abstract: A system on a chip (SOC) includes a critical domain including components configured to perform critical operations and a non-critical domain including components configured to perform non-critical operations. To help perform such operations, the critical domain and non-critical domain share a static random-access memory (SRAM) that includes a first subset of memory banks assigned to the critical domain and a second subset of memory banks assigned to the non-critical domain. The SOC further includes a memory scrubbing circuitry configured to sequentially check each memory bank of the SRAM for errors. To this end, the memory scrubbing circuitry is configured to check a respective memory bank for errors each time an event trigger occurs by implementing one or more error correction codes.

    DATA COLLECTION AND STORAGE DURING LOW-POWER STATES
    2.
    发明申请
    DATA COLLECTION AND STORAGE DURING LOW-POWER STATES 有权

    公开(公告)号：US20250138749A1

    公开(公告)日：2025-05-01

    申请号：US18385117

    申请日：2023-10-30

    Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

    Inventor： I-Cheng Chen ,  Pankaj Sen

    IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3296

    Abstract: A processing system includes one or more sensors configured to generate sensor data while a memory of the processing system is in a low-power state. As the sensors generate the sensor data, the sensor data is stored in a buffer. The processing system further includes a sensor data management circuitry that tracks a usage of the buffer. Based on the usage of the buffer exceeding a threshold, the sensor data management circuitry is configured to wake at least a portion of the memory from the low-power state. Once the memory exits the low-power state, the processing system transfers the sensor data from the buffer to one or more locations within the memory. After writing the sensor data to the memory, the processing system then places at least a portion of the memory back in the low-power state.

    Alternative protocol over physical layer
    3.
    发明授权
    Alternative protocol over physical layer 有权

    公开(公告)号：US12287753B2

    公开(公告)日：2025-04-29

    申请号：US18216908

    申请日：2023-06-30

    Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

    Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

    IPC: G06F13/20 ,  G06F13/16 ,  G06F13/42

    Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

    Default boost mode state for devices
    4.
    发明授权
    Default boost mode state for devices 有权

    公开(公告)号：US12277020B2

    公开(公告)日：2025-04-15

    申请号：US17561837

    申请日：2021-12-24

    Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

    Inventor： Joseph Lee Greathouse ,  Adam Neil Calder Clark ,  Stephen Kushnir

    IPC: G06F1/3296 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/324

    Abstract: One or more components of a computing device are run by default in a boost mode state. The one or more components continue to run in the boost mode state until the boost mode state is no longer sustainable, e.g., due to power consumption of the one or more components or temperature of the one or more components. The one or more components are switched to a reduced power state (e.g., a non-boost mode state) in response to the boost mode state no longer being sustainable. When operating the one or more components in the boost mode state again becomes sustainable due to power consumption or temperature of the one or more components, the one or more components are returned to the default boost mode state.

    Fused Bounding Volume Hierarchy for Multiple Levels of Detail
    5.
    发明申请
    Fused Bounding Volume Hierarchy for Multiple Levels of Detail 有权

    公开(公告)号：US20250111606A1

    公开(公告)日：2025-04-03

    申请号：US18375046

    申请日：2023-09-29

    Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

    Inventor： Paritosh Vijay Kulkarni ,  Ikeda Sho ,  Takahiro Harada

    IPC: G06T17/00 ,  G06T17/20

    Abstract: A fused bounding volume hierarchy, which is a combination of a base bounding volume hierarchy and one or more non-base bounding volume hierarchies, is generated. For each non-base bounding volume hierarchy, multiple subtrees in the non-base bounding volume hierarchy that include less than a threshold number of child nodes are identified. Each of these subtrees is then fused with the base bounding volume hierarchy at one of the nodes of the base bounding volume hierarchy, and an identifier of the level of detail for the non-base bounding volume hierarchy is included in the node. When displaying a scene or image, for a particular portion of the scene or image the level of detail to use is identified. The fused bounding volume hierarchy is traversed and the geometric objects in the nodes of the fused bounding volume hierarchy corresponding to the identified level of detail are displayed.

    HYBRID DEFERRED DECOUPLED RENDERING
    6.
    发明申请
    HYBRID DEFERRED DECOUPLED RENDERING 有权

    公开(公告)号：US20250111598A1

    公开(公告)日：2025-04-03

    申请号：US18477375

    申请日：2023-09-28

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Michal Adam Wozniak ,  Guennadi Riguer

    IPC: G06T15/80 ,  G06T15/04

    Abstract: A technique for rendering is provided. The technique includes performing a visibility operation to generate shade space visibility information and reconstruction information; performing a shade space shading operation based on the shade space visibility information generate shaded shade space textures; and performing a reconstruction operation based on the reconstruction information and the shaded shade space textures.

    DEVICES, SYSTEMS, AND METHODS FOR DYNAMICALLY CHANGING FREQUENCIES OF CLOCKS FOR THE DATA LINK LAYER WITHOUT DOWNTIME
    10.
    发明申请
    DEVICES, SYSTEMS, AND METHODS FOR DYNAMICALLY CHANGING FREQUENCIES OF CLOCKS FOR THE DATA LINK LAYER WITHOUT DOWNTIME 有权

    公开(公告)号：US20250103090A1

    公开(公告)日：2025-03-27

    申请号：US18476082

    申请日：2023-09-27

    Applicant: ATI Technologies ULC

    Inventor： Shaofeng An ,  YanFeng Wang

    IPC: G06F1/08

    Abstract: An exemplary method for dynamically changing frequencies of clocks for the data link layer without downtime involves switching a first queue on a first end of a data link and a second queue on a second end of the data link from a pacing mode to an asynchronous mode. The exemplary method also involves modifying a frequency of a clock associated with the data link. The exemplary method further involves returning the first queue and the second queue from the asynchronous mode to the pacing mode upon modifying the frequency of the clock. Various other devices, systems, and methods are also disclosed.

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