公开(公告)号：US12192079B2

公开(公告)日：2025-01-07

申请号：US18202899

申请日：2023-05-27

Applicant: Microchip Technology Inc.

Inventor： Scott Muma ,  Winston Mok ,  Steven Scott Gorshe

IPC: H04L43/062 ,  H04L43/0894 ,  H04L7/04 ,  H04L12/70

Abstract: A method and apparatus in which a data stream is received that includes constant bit rate (CBR) carrier streams, at least one of which comprises frames, a cumulative phase offset report (CPOR) and a client rate report (CRR). A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD). The data stream is demultiplexed to obtain CBR carrier streams. Respective CBR carrier streams include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

公开(公告)号：US12154622B2

公开(公告)日：2024-11-26

申请号：US17736563

申请日：2022-05-04

Applicant: Microchip Technology Inc.

Inventor： Victor Nguyen ,  Fethi Dhaoui ,  John L McCollum ,  Fengliang Xue

IPC: G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: A ReRAM memory array includes ReRAM memory cells having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors of the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors of the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.

公开(公告)号：US11860022B2

公开(公告)日：2024-01-02

申请号：US17336068

申请日：2021-06-01

Applicant: Microchip Technology Incorporated

Inventor： Lorenzo Bellina ,  Maurizio Fiammeni

IPC: G01F23/26 ,  G01F23/263 ,  G01D5/24

CPC classification number: G01F23/263 ,  G01D5/2405

Abstract: One or more examples relate to a detector. A signal that the detector is configured to sense is a differential value. Such a differential value may be indicative of a difference in self-capacitance indications that are exhibited at first and second internal capacitors. Such a differential value may be proportional to a relationship between a first material and a second material present at a device-under-test coupled to electrodes of the detector. Such a differential value may be proportional to a vertical elevation of a surface of a material present at a device-under-test coupled to electrodes of the detector. A difference in coupling capacitances may be obtained by performing complimentary acquisition processes utilizing symmetric capacitive sensors. When the acquisition processes are performed substantially simultaneously, coupling error indications that may be present in the self-capacitance indications are not present in the differential value.

公开(公告)号：US11799626B2

公开(公告)日：2023-10-24

申请号：US17885194

申请日：2022-08-10

Applicant: Microchip Technology Inc.

Inventor： Scott Muma ,  Winston Mok ,  Steven Scott Gorshe

IPC: H04L7/04 ,  H04J3/06 ,  H04L12/70

CPC classification number: H04L7/04 ,  H04J3/0658 ,  H04L2012/5674

Abstract: A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

公开(公告)号：US11659099B2

公开(公告)日：2023-05-23

申请号：US16446498

申请日：2019-06-19

Applicant: Microchip Technology Inc.

Inventor： Renato Colombo ,  Cesare Bocchiola

IPC: G06F1/26 ,  H02M7/493 ,  H02M5/10 ,  H04M19/08 ,  H02M3/335 ,  G05F1/66

CPC classification number: H04M19/08 ,  G06F1/263 ,  H02M3/33569 ,  H02M5/10 ,  H02M7/493 ,  G05F1/66

Abstract: A reverse power feeding (RPF) power supply unit (PSU) for remote network distribution point unit (DPU) that is reverse powered from multiple customer premise equipments (CPEs). A plurality of power converters, each having a different primary winding and sharing a common secondary winding of a transformer at the PSU, wherein only one of the power converters is operated at a time to provide a desired output voltage.

公开(公告)号：US11658911B2

公开(公告)日：2023-05-23

申请号：US17383755

申请日：2021-07-23

Applicant: Microchip Technology Inc.

Inventor： Morten Terstrup

IPC: H04L47/2425 ,  H04L47/28 ,  H04L49/00 ,  H04L47/625 ,  H04L45/745

CPC classification number: H04L47/2433 ,  H04L45/74591 ,  H04L47/28 ,  H04L47/625 ,  H04L49/3018

Abstract: A network switch and associated method of operation for establishing a low latency transmission path through the network which bypasses the packet queue and scheduler of the switch fabric. The network switch transmits each of a plurality of data packets to the identified destination egress port over the low latency transmission if the data packet is identified to be transmitted over the low latency transmission path from the ingress port to the destination egress port, and transmits the data packet to the destination egress port through the packet queue and scheduler if the data packet is not identified to be transmitted over the low latency transmission path from the ingress port to the destination egress ports.

公开(公告)号：US11656101B2

公开(公告)日：2023-05-23

申请号：US17146875

申请日：2021-01-12

Applicant: Microchip Technology Inc.

Inventor： Ganesh Shaga

IPC: G01D5/20 ,  G01B7/30

CPC classification number: G01D5/2073 ,  G01B7/30

Abstract: A redundant angular position sensor comprising a first angular position sensor including a first excitation coil, a first sensing coil and a second sensing coil and a second angular position sensor. The second angular position sensor including a second excitation coil, a third sensing coil and a fourth sensing coil. Each of the first, second, third and fourth sensing coils comprising a respective clockwise winding portion and a respective counter-clockwise winding portion. The redundant angular position sensor further comprises a rotatable inductive coupling element positioned in overlying relation to the sensing coils and separated from the sensing coils by a gap, wherein the rotatable inductive coupling element comprises four, substantially evenly radially spaced, sector apertures.

公开(公告)号：US20220382688A1

公开(公告)日：2022-12-01

申请号：US17741282

申请日：2022-05-10

Applicant: Microchip Technology Inc.

Inventor： Sanjay GOYAL ,  Larrie Simon Carr ,  Patrick Bailey

IPC: G06F13/16 ,  G06F13/42 ,  G06F11/10

Abstract: System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.

公开(公告)号：US20220342668A1

公开(公告)日：2022-10-27

申请号：US17468574

申请日：2021-09-07

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F9/30 ,  G06F9/38

Abstract: In one implementation devoid of an effective address generator a method of call operation comprises pushing one or more parameters onto a first stack, pushing the contents of one or more registers onto a second stack, popping off the first stack one or more of the parameters into one or more of the registers whose contents were pushed onto the second stack, performing register to register operations on the one or more registers whose contents were pushed onto the second stack with a result of the register to register operations being stored in a result register, the result register being one of the one or more registers whose contents were pushed onto the second stack, popping off the second stack the contents of all the one or more registers into their respective registers from which they came, and returning control to an instruction following the call.

公开(公告)号：US20220342582A1

公开(公告)日：2022-10-27

申请号：US17671423

申请日：2022-02-14

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: G06F3/06

Abstract: A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.