公开(公告)号：US20200321243A1

公开(公告)日：2020-10-08

申请号：US16301276

申请日：2017-05-17

申请人： SOITEC

发明人： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC分类号： H01L21/762

摘要： A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US20190221471A1

公开(公告)日：2019-07-18

申请号：US16324461

申请日：2017-08-01

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives ,  Boitec

发明人： Didier Landru ,  Nadia Ben Mohamed ,  Oleg Kononchuk ,  Frederic Mazen ,  Damien Massy ,  Shay Reboh ,  Francois Rieutord

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： A useful layer is layered onto a support by a method that includes the steps of forming an embrittlement plane by implanting light elements into a first substrate, so as to form a useful layer between such plane and one surface of the first substrate; applying the support onto the surface of the first substrate so as to form an assembly to be fractured; applying a heat treatment for embrittling the assembly to be fractured; and initiating and propagating a fracture wave into the first substrate along the embrittlement plane. The fracture wave is initiated in a central area of the embrittlement plane and the propagation speed of the wave is controlled so that the velocity thereof is sufficient to cause the interactions of the fracture wave with acoustic vibrations emitted upon the initiation and/or propagation thereof, if any, are confined to a peripheral area of the useful layer.

公开(公告)号：US20190088462A1

公开(公告)日：2019-03-21

申请号：US15743004

申请日：2016-07-13

申请人： Soitec

发明人： Pascal Guenard ,  Marcel Broekaart ,  Thierry Barge

IPC分类号： H01L21/02 ,  H01L41/083 ,  H01L41/312 ,  H01L41/187

摘要： A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.

公开(公告)号：US20190058031A1

公开(公告)日：2019-02-21

申请号：US16080279

申请日：2017-02-23

申请人： Centre National de la Recherche Scientifque ,  Universite Claude Bernard Lyon 1 ,  Soitec

发明人： Christophe Figuet ,  Oleg Kononchuk ,  Kassam Alassaad ,  Gabriel Ferro ,  Véronique Souliere ,  Christelle Veytizou ,  Taguhi Yeghoyan

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L29/16 ,  H01L21/02

摘要： A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.

公开(公告)号：US08253170B2

公开(公告)日：2012-08-28

申请号：US13108944

申请日：2011-05-16

申请人： Hacène Lahreche

发明人： Hacène Lahreche

IPC分类号： H01L31/0328 ,  H01L29/80 ,  H01L31/112 ,  H01L29/778

CPC分类号： H01L29/452 ,  H01L21/28575 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/778

摘要： In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s).

摘要翻译： 在一个实施例中，本发明涉及从其基底到其表面连续地包括的电子设备：（a）支撑层，（b）适于容纳电子气的沟道层，（c）阻挡层和（d） 至少一个欧姆接触电极，通过叠加金属层形成，其第一层与阻挡层接触。 该器件是显着的，因为阻挡层包括在欧姆接触电极下的接触区域。 接触区域包括选自形成金属层叠加的金属中的至少一种金属。 此外，局部合金化结合电极的接触区域和第一层。

公开(公告)号：US20240312831A1

公开(公告)日：2024-09-19

申请号：US18566474

申请日：2022-05-25

申请人： SOITEC ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Alexis Drouin ,  Gweltaz Gaudin ,  Séverin Rouchier ,  Walter Schwarzenbach ,  Julie Widiez ,  Emmanuel Rolland

IPC分类号： H01L21/762 ,  H01L21/04

CPC分类号： H01L21/76254 ,  H01L21/0445

摘要： A method for producing a semiconductor structure comprises: a) provision of a monocrystalline silicon carbide donor substrate and a silicon carbide support substrate; b) production of a useful layer to be transferred, comprising—implanting light species in the donor substrate at a front face, so as to form a damage profile, the profile having a main peak of deep-level defects defining a buried brittle plane and a secondary peak of defects defining a damaged surface layer, and—removing the damaged surface layer by chemical etching and/or chemical mechanical polishing of the front face of the donor substrate, so as to form a new front surface of the donor substrate; c) assembly of donor substrate with the support substrate; and d) separation along the buried fragile plane, leading to the transfer of the useful layer onto the support substrate, so as to form the semiconductor structure.

公开(公告)号：US20240290615A1

公开(公告)日：2024-08-29

申请号：US18647252

申请日：2024-04-26

申请人： Soitec

发明人： Young-Pil Kim

IPC分类号： H01L21/02 ,  C23C16/24 ,  C23C16/26 ,  C23C16/44

CPC分类号： H01L21/02658 ,  C23C16/24 ,  C23C16/26 ,  C23C16/4404 ,  C23C16/4405 ,  H01L21/02238

摘要： A support for a semiconductor structure comprises a base substrate and a charge trapping layer on the base substrate. The charge trapping layer comprises an alternating stack of at least one polycrystalline charge trapping material and at least one polycrystalline interlayer. The charge trapping material has a grain size between 100 nanometers (nm) and 1000 nm, and/or a lattice parameter greater than a lattice parameter of the at least one interlayer. Also disclosed is a semiconductor structure comprising such support.

公开(公告)号：US12074056B2

公开(公告)日：2024-08-27

申请号：US18047113

申请日：2022-10-17

申请人： Soitec

发明人： Walter Schwarzenbach

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

CPC分类号： H01L21/76254 ,  H01L21/84 ,  H01L27/1207 ,  H01L21/02532

摘要： A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.

公开(公告)号：US20240170284A1

公开(公告)日：2024-05-23

申请号：US18550044

申请日：2022-03-03

申请人： Soitec

发明人： Gweltaz Gaudin ,  Christophe Maleville ,  lonut Radu ,  Hugo Biard

IPC分类号： H01L21/02 ,  C23C16/02 ,  C23C16/32 ,  C23C16/56 ,  H01L21/762

CPC分类号： H01L21/02529 ,  C23C16/0227 ,  C23C16/325 ,  C23C16/56 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/76254

摘要： A method for producing a semiconductor structure, comprises: a) providing a temporary substrate made of graphite having a grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a coefficient of thermal expansion of between 4×10-6/° C. and 5×10-6/° C.; b) depositing, on a front face of the temporary substrate, a carrier layer made of polycrystalline silicon carbide having a thickness of between 10 microns and 200 microns, c) transferring a working layer made of monocrystalline silicon carbide to the carrier layer to form a composite structure, the transfer implementing bonding by molecular adhesion, d) forming an active layer on the working layer, e) and removing the temporary substrate to form the semiconductor structure, the structure including the active layer, the working layer and the carrier layer. A composite structure is obtained in an intermediate step of the production method.

公开(公告)号：US11979132B2

公开(公告)日：2024-05-07

申请号：US17042016

申请日：2019-03-27

申请人： Soitec

发明人： Djamel Belhachemi ,  Thierry Barge

IPC分类号： H03H3/02 ,  H10N30/00 ,  H10N30/05 ,  H10N30/073 ,  H10N30/853

CPC分类号： H03H3/02 ,  H10N30/05 ,  H10N30/073 ,  H10N30/10516 ,  H10N30/8542 ,  Y10T29/42

摘要： A method for manufacturing a substrate for a radiofrequency filter by joining a piezoelectric layer to a carrier substrate via an electrically insulating layer, wherein the method comprises depositing the electrically insulating layer by spin coating an oxide belonging to the family of SOGs (spin-on glasses) on the surface of the piezoelectric layer to be joined to the carrier substrate, followed by an anneal for densifying the electrically insulating layer before joining the piezoelectric layer to the carrier substrate via the electrically insulating layer.