公开(公告)号：US20050104647A1

公开(公告)日：2005-05-19

申请号：US10987430

申请日：2004-11-12

Applicant: Chul Choi ,  Jae-Goo Lee ,  Byung-Hun Han

Inventor： Chul Choi ,  Jae-Goo Lee ,  Byung-Hun Han

IPC: G09G3/36 ,  G02F1/133 ,  G06F1/04 ,  G09G3/20 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185 ,  H04N5/66

CPC classification number: G06F1/04

Abstract: Provided are a level shifter circuit and a corresponding method for controlling voltage levels of a clock signal and an inverted clock signal for driving gate lines of a ASG thin film transistor liquid crystal display panel, where the level shifter circuit includes first and second level shifters, the first level shifter controls the voltage level of the clock signal to swing between a negative external voltage level and a positive external voltage level in response to a clock activating signal, and increases the voltage level of the clock signal from the negative external voltage level to a power supply voltage level or decreases it from the positive external voltage level to a ground voltage level while a pre-charge clock activating signal is activated, the second level shifter controls the voltage level of the inverted clock signal to swing between the negative external voltage level and the positive external voltage level in response to an inverted clock activating signal, and increases the voltage level of the inverted clock signal from the negative external voltage level to the power supply voltage level or decreases it from the positive external voltage level to the ground voltage level while an inverted pre-charge clock activating signal is activated, and the level shifter circuit increases or decreases the voltage levels of the clock signal and inverted clock signal using a battery voltage or a ground voltage, thereby reducing current consumption caused by the increase or decrease in the voltage level.

Abstract translation: 提供了一种用于控制用于驱动ASG薄膜晶体管液晶显示面板的栅极线的时钟信号和反相时钟信号的电压电平的电平移位器电路和相应方法，其中电平移位器电路包括第一和第二电平移位器， 第一电平移位器响应于时钟激活信号控制时钟信号的电压电平在负的外部电压电平和正的外部电压电平之间摆动，并且将时钟信号的电压电平从负的外部电压电平提高到 电源电压电平或者从正的外部电压电平降低到接地电压电平，同时预充电时钟激活信号被激活，第二电平移位器控制反相时钟信号的电压电平在负外部电压之间摆动 电平和正的外部电压电平响应于反相时钟激活信号，并且包括 将反相时钟信号的电压电平从负外部电压电平降低到电源电压电平，或将其从正外部电压电平降低到接地电压电平，同时反相的预充电时钟激活信号被激活，并且电平 移位器电路使用电池电压或接地电压来增加或减少时钟信号和反相时钟信号的电压电平，由此降低由电压电平的增加或减少引起的电流消耗。

公开(公告)号：US20120206506A1

公开(公告)日：2012-08-16

申请号：US13396043

申请日：2012-02-14

Applicant: In-Suk Kim ,  Jae Goo Lee ,  Byung Hun Han

Inventor： In-Suk Kim ,  Jae Goo Lee ,  Byung Hun Han

IPC: G06F3/038 ,  G09G5/10

CPC classification number: G09G3/20 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2310/0251 ,  G09G2310/027

Abstract: A source driver, a display device including the same, and a method of driving the display device are provided. The source driver includes a global block configured to output “k” global gamma voltage signals, where “k” is 2 or an integer greater than 2. Each “k” global gamma voltage signal comprises a plurality of grayscale voltages and a pre-emphasis voltage that is output from the global block prior to each of the plurality of grayscale voltages. A channel driver is configured to select a global gamma voltage signal of the “k” global gamma voltage signals. The selected global gamma voltage signal includes a grayscale voltage of the plurality of grayscale voltages. The channel driver outputs the grayscale voltage to a source line in response to the channel driver receiving image data.

Abstract translation: 提供源驱动器，包括其的显示装置和驱动显示装置的方法。 源驱动器包括被配置为输出“k”个全局伽马电压信号的全局块，其中“k”为2或大于2的整数。“k”全局伽马电压信号包括多个灰度电压和预加重 电压，其在所述多个灰度级电压中的每一个之前从所述全局块输出。 通道驱动器被配置为选择“k”全局γ电压信号的全局γ电压信号。 所选择的全局γ电压信号包括多个灰度电压的灰度电压。 通道驱动器响应于通道驱动器接收图像数据而将灰度电压输出到源极线。

公开(公告)号：US07466312B2

公开(公告)日：2008-12-16

申请号：US10987430

申请日：2004-11-12

Applicant: Chul Choi ,  Jae-Goo Lee ,  Byung-Hun Han

Inventor： Chul Choi ,  Jae-Goo Lee ,  Byung-Hun Han

IPC: G09G3/36 ,  G09G3/38

CPC classification number: G06F1/04

Abstract: Provided are a level shifter circuit and a corresponding method for controlling voltage levels of a clock signal and an inverted clock signal for driving gate lines of a ASG thin film transistor liquid crystal display panel, where the level shifter circuit includes first and second level shifters, the first level shifter controls the voltage level of the clock signal to swing between a negative external voltage level and a positive external voltage level in response to a clock activating signal, and increases the voltage level of the clock signal from the negative external voltage level to a power supply voltage level or decreases it from the positive external voltage level to a ground voltage level while a pre-charge clock activating signal is activated, the second level shifter controls the voltage level of the inverted clock signal to swing between the negative external voltage level and the positive external voltage level in response to an inverted clock activating signal, and increases the voltage level of the inverted clock signal from the negative external voltage level to the power supply voltage level or decreases it from the positive external voltage level to the ground voltage level while an inverted pre-charge clock activating signal is activated, and the level shifter circuit increases or decreases the voltage levels of the clock signal and inverted clock signal using a battery voltage or a ground voltage, thereby reducing current consumption caused by the increase or decrease in the voltage level.

Abstract translation: 提供了一种用于控制用于驱动ASG薄膜晶体管液晶显示面板的栅极线的时钟信号和反相时钟信号的电压电平的电平移位器电路和相应方法，其中电平移位器电路包括第一和第二电平移位器， 第一电平移位器响应于时钟激活信号控制时钟信号的电压电平在负的外部电压电平和正的外部电压电平之间摆动，并且将时钟信号的电压电平从负的外部电压电平提高到 电源电压电平或者从正的外部电压电平降低到接地电压电平，同时预充电时钟激活信号被激活，第二电平移位器控制反相时钟信号的电压电平在负外部电压之间摆动 电平和正的外部电压电平响应于反相时钟激活信号，并且包括 将反相时钟信号的电压电平从负外部电压电平降低到电源电压电平，或将其从正外部电压电平降低到接地电压电平，同时反相的预充电时钟激活信号被激活，并且电平 移位器电路使用电池电压或接地电压来增加或减少时钟信号和反相时钟信号的电压电平，由此降低由电压电平的增加或减少引起的电流消耗。

公开(公告)号：US20070121395A1

公开(公告)日：2007-05-31

申请号：US11560035

申请日：2006-11-15

Applicant: Sang-hun Kim ,  Byung-hun Han ,  Kyung-myun Kim

Inventor： Sang-hun Kim ,  Byung-hun Han ,  Kyung-myun Kim

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G09G3/20 ,  G09G2310/08 ,  G09G2320/10 ,  G09G2330/021 ,  G09G2360/18 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222

Abstract: A source driver control device and method. The source driver control device includes a memory, a first write controller, a second write controller and a write clock signal generator. The memory receives display data corresponding to an image and stores the display data in response to a write clock signal. The first write controller generates a first write enable signal in response to a vertical back porch and a horizontal back porch. The second write controller generates a second write enable signal, which is enabled for each write cycle of storing the display data in the memory, in response to the first write enable signal. The write clock signal generator generates the write clock signal in a period in which the second write enable signal is enabled. The write cycle corresponds to a multiple of a reference write cycle. The source driver control device and method can reduce power consumed when the display data is written in the memory.

Abstract translation: 源驱动器控制装置和方法。 源极驱动器控制装置包括存储器，第一写入控制器，第二写入控制器和写入时钟信号发生器。 存储器接收对应于图像的显示数据并且响应于写入时钟信号存储显示数据。 第一写入控制器响应于垂直后门廊和水平后门廊而生成第一写入使能信号。 第二写入控制器响应于第一写入使能信号而产生第二写入使能信号，该第二写入使能信号被用于将存储显示数据的每个写周期存储在存储器中。 写入时钟信号发生器在第二写使能信号被使能的时段中产生写入时钟信号。 写周期对应于参考写周期的倍数。 源驱动器控制装置和方法可以在显示数据写入存储器时减少消耗的功率。

公开(公告)号：US6100769A

公开(公告)日：2000-08-08

申请号：US274401

申请日：1999-03-23

Applicant: Byung-Kwon An ,  Byung-Hun Han

Inventor： Byung-Kwon An ,  Byung-Hun Han

IPC: H03K3/0231 ,  H03K3/03 ,  H03B5/02

CPC classification number: H03K3/03 ,  H03K3/0231 ,  H03K3/0322

Abstract: A differential delay circuit type ring oscillator allows for an increase in operation enabling frequency and dynamic range. At each stage of the ring, delay circuit output signals arc linearly varied above and below the circuit switching level. The ring oscillator includes a plurality of differential delay circuits coupled in series in a ring configuration, a differential amplifier, and a comparator. Each of the differential delay circuits receives first and second differential input signals, and delays the received signals by a predetermined time in response to a predetermined control signal to generate first and second differential output signals. The differential amplifier receives the first and the second differential output signals of one of the differential delay circuits and amplifies the received signals to generate first and second differential amplified signals. The comparator receives first and the second differential amplified signals, and compares them to generate an oscillating signal in accordance with the comparison results.

Abstract translation: 差分延迟电路型环形振荡器允许增加工作频率和动态范围。 在环的每个阶段，延迟电路输出信号在电路开关电平之上和之下呈线性变化。 环形振荡器包括以环形配置串联耦合的多个差分延迟电路，差分放大器和比较器。 每个差分延迟电路接收第一和第二差分输入信号，并且响应于预定控制信号将接收信号延迟预定时间以产生第一和第二差分输出信号。 差分放大器接收差分延迟电路之一的第一和第二差分输出信号，并放大接收信号以产生第一和第二差分放大信号。 比较器接收第一和第二差分放大信号，并根据比较结果进行比较以产生振荡信号。

公开(公告)号：US09093038B2

公开(公告)日：2015-07-28

申请号：US12784200

申请日：2010-05-20

Applicant: Byung-hun Han ,  Jae-goo Lee

Inventor： Byung-hun Han ,  Jae-goo Lee

IPC: G09G3/36 ,  G09G3/32

CPC classification number: G09G3/3614 ,  G09G3/3648 ,  G09G3/3696 ,  G09G2330/02

Abstract: A voltage stabilizer circuit for alternately or simultaneously stabilizing first and second generated voltages includes shared capacitor connected between the first and second generated voltages. The voltage stabilizer circuit may further include first and second switches for alternately connecting the first and second electrode of the shared capacitor to a ground. The alternation of the stabilized first and second voltages output by the voltage stabilizer circuit can be synchronized with a pixel polarity inversion mode signal output by the internal driver circuit of an LCD display.

Abstract translation: 用于交替或同时稳定第一和第二产生电压的稳压器电路包括连接在第一和第二产生电压之间的共享电容器。 电压稳定器电路还可以包括用于将共享电容器的第一和第二电极交替地连接到地的第一和第二开关。 由稳压器电路输出的稳定的第一和第二电压的交替可与由LCD显示器的内部驱动电路输出的像素极性反转模式信号同步。

公开(公告)号：US08599184B2

公开(公告)日：2013-12-03

申请号：US12815520

申请日：2010-06-15

Applicant: Byung-hun Han ,  Sung-jin Park

Inventor： Byung-hun Han ,  Sung-jin Park

IPC: G09G5/00

CPC classification number: H02M3/073

Abstract: Provided is a boosting voltage generating element used in a semiconductor integrated circuit, more particularly, is a charge pump. The charge pump includes a first converting unit and a second converting unit. The first converting unit is configured to receive a first voltage in response to a first clock signal to generate a first pumping voltage. The first converting unit is also configured to alternately output the first pumping voltage to a first terminal and a second terminal. The second converting unit is configured to receive the first pumping voltage through the first terminal or the second terminal in response to a second clock signal and a third clock signal respectively, to generate a second pumping voltage The second converting unit is also configured to provide the second pumping voltage to an output terminal. The second converting unit is configured to provide the second pumping voltage to the output terminal for at least half of a period of the second clock signal or the third clock signal.

Abstract translation: 提供了一种用于半导体集成电路中的升压电压产生元件，更具体地，是电荷泵。 电荷泵包括第一转换单元和第二转换单元。 第一转换单元被配置为响应于第一时钟信号接收第一电压以产生第一泵浦电压。 第一转换单元还被配置为交替地将第一泵送电压输出到第一端子和第二端子。 第二转换单元被配置为响应于第二时钟信号和第三时钟信号分别接收通过第一端子或第二端子的第一泵浦电压，以产生第二泵浦电压。第二转换单元还被配置为提供 第二泵送电压到输出端子。 第二转换单元被配置为在第二时钟信号或第三时钟信号的周期的至少一半内向输出端提供第二泵浦电压。

公开(公告)号：US20130057530A1

公开(公告)日：2013-03-07

申请号：US13563295

申请日：2012-07-31

Applicant: Byung-Hun HAN ,  Kyung-Hoon CHUNG

Inventor： Byung-Hun HAN ,  Kyung-Hoon CHUNG

IPC: G09G5/00

CPC classification number: G09G3/3696 ,  G09G2330/021 ,  G09G2330/026 ,  G09G2330/028 ,  H02M3/07 ,  H02M3/155

Abstract: A power converting circuit of a display driver includes a positive voltage generator and a negative voltage generator. The positive voltage generator includes a first capacitive DC-DC converter and a first inductive DC-DC converter, and generates a positive source voltage by selectively using one of the first capacitive DC-DC converter, the first inductive DC-DC converter, or a first external power supply voltage. The negative voltage generator includes a second capacitive DC-DC converter and a second inductive DC-DC converter, and generates a negative source voltage by selectively using one of the second capacitive DC-DC converter, the second inductive DC-DC converter, or a second external power supply voltage.

Abstract translation: 显示驱动器的电力转换电路包括正电压发生器和负电压发生器。 正电压发生器包括第一电容DC-DC转换器和第一电感DC-DC转换器，并且通过选择性地使用第一电容DC-DC转换器，第一电感DC-DC转换器或 第一个外部电源电压。 负电压发生器包括第二电容DC-DC转换器和第二电感DC-DC转换器，并且通过选择性地使用第二电容DC-DC转换器，第二电感DC-DC转换器或 第二个外部电源电压。

公开(公告)号：US20110115834A1

公开(公告)日：2011-05-19

申请号：US12815520

申请日：2010-06-15

Applicant: Byung-hun HAN ,  Sung-jin Park

Inventor： Byung-hun HAN ,  Sung-jin Park

IPC: G09G5/10 ,  G05F3/02

CPC classification number: H02M3/073

Abstract: Provided is a boosting voltage generating element used in a semiconductor integrated circuit, more particularly, is a charge pump. The charge pump includes a first converting unit and a second converting unit. The first converting unit is configured to receive a first voltage in response to a first clock signal to generate a first pumping voltage. The first converting unit is also configured to alternately output the first pumping voltage to a first terminal and a second terminal. The second converting unit is configured to receive the first pumping voltage through the first terminal or the second terminal in response to a second clock signal and a third clock signal respectively, to generate a second pumping voltage The second converting unit is also configured to provide the second pumping voltage to an output terminal. The second converting unit is configured to provide the second pumping voltage to the output terminal for at least half of a period of the second clock signal or the third clock signal.

Abstract translation: 提供了一种用于半导体集成电路中的升压电压产生元件，更具体地，是电荷泵。 电荷泵包括第一转换单元和第二转换单元。 第一转换单元被配置为响应于第一时钟信号接收第一电压以产生第一泵浦电压。 第一转换单元还被配置为交替地将第一泵送电压输出到第一端子和第二端子。 第二转换单元被配置为响应于第二时钟信号和第三时钟信号分别接收通过第一端子或第二端子的第一泵浦电压，以产生第二泵浦电压。第二转换单元还被配置为提供 第二泵送电压到输出端子。 第二转换单元被配置为在第二时钟信号或第三时钟信号的周期的至少一半内向输出端提供第二泵浦电压。

公开(公告)号：US06172516B2

公开(公告)日：2001-01-09

申请号：US09351075

申请日：1999-07-09

Applicant: Byung-hun Han ,  Byung-kwon An

Inventor： Byung-hun Han ,  Byung-kwon An

IPC: H03K1716

CPC classification number: H03K17/164

Abstract: An output buffer capable of reducing the noise and distortion of buffered output data while operating at high speed, and a buffering method performed in the output buffer are provided. An output buffer for buffering input data and outputting buffered input data as output data comprises first through M-th and (M+1)th through (M+N)th delay means for delaying the input data for (M+N) different delay times and outputting one by one delayed data in a predetermined order at time intervals of T M + N , where M and N are each integers equal to or greater than 2, and T corresponds to the time necessary for the level of the output data to change, and a data output means for outputting the output data in response to the outputs of the first through (M+N)th delay means.

Abstract translation: 一种输出缓冲器，其能够在高速运行的同时降低缓冲输出数据的噪声和失真，并提供在输出缓冲器中执行的缓冲方法。 用于缓冲输入数据并输出缓冲输入数据作为输出数据的输出缓冲器包括第一至第M和第（M + 1）至第（M + N）个延迟装置，用于将输入数据延迟（M + N）个不同延迟 时间，并且以其中M和N的时间间隔以预定顺序逐个输出延迟数据，每个整数等于或大于2，并且T对应于输出数据的电平变化所需的时间，以及数据输出 用于响应于第一至第（M + N）个延迟装置的输出而输出输出数据的装置。