公开(公告)号：US08502324B2

公开(公告)日：2013-08-06

申请号：US12581549

申请日：2009-10-19

Applicant: Victor Pol ,  Chong-Cheng Fu

Inventor： Victor Pol ,  Chong-Cheng Fu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.

Abstract translation: 提供包括至少第一管芯和至少第二管芯的晶片，其中所述第一管芯和所述第二管芯彼此分开位于所述第一管芯和所述第二管芯之间的区域。 晶片还包括用于将晶片对准用于图案化晶片的工具的对准标记组。 对准标记组完全位于第一管芯和第二管芯之间的区域内，并且对准标记组包括多个对准线，并且其中多个对准线中的每条线使用与每个对准线分离的多个段形成 另外由填充绝缘材料的多个间隙。

公开(公告)号：US07235473B2

公开(公告)日：2007-06-26

申请号：US11213470

申请日：2005-08-26

Applicant: Dharmesh Jawarani ,  Chong-Cheng Fu ,  Mark D. Hall

Inventor： Dharmesh Jawarani ,  Chong-Cheng Fu ,  Mark D. Hall

IPC: H01L21/4763

CPC classification number: H01L29/66507

Abstract: A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.

公开(公告)号：US07132327B2

公开(公告)日：2006-11-07

申请号：US10853701

申请日：2004-05-25

Applicant: Tab A. Stephens ,  Chong-Cheng Fu ,  Charles F. King

Inventor： Tab A. Stephens ,  Chong-Cheng Fu ,  Charles F. King

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/32139 ,  H01L21/28123

Abstract: A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM), then etching a cut mask for a cPSM mask. Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning steps which form combined patterns through the use of partial image transfers into an intermediate hard mask prior to final wafer patterning. The intermediate and final hard mask materials are chosen to prevent image transfer into an underlying substrate or wafer prior to the final etch process.

Abstract translation: 图案化方法允许互补掩模版集合的单独转移。 在一个实施例中，例如，该方法包括蚀刻相移掩模（PSM），然后蚀刻用于cPSM掩模的切割掩模。 此外，解耦互补掩模图案转移方法包括两个单独的和去耦的掩模图案化步骤，其通过在最终的晶片图案化之前通过使用部分图像转移到中间硬掩模中形成组合图案。 选择中间和最终硬掩模材料以防止在最终蚀刻工艺之前图像转移到下面的基底或晶片中。

公开(公告)号：US20050277276A1

公开(公告)日：2005-12-15

申请号：US10853701

申请日：2004-05-25

Applicant: Tab Stephens ,  Chong-Cheng Fu ,  Charles King

Inventor： Tab Stephens ,  Chong-Cheng Fu ,  Charles King

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/4763 ,  H01L21/8222

CPC classification number: H01L21/32139 ,  H01L21/28123

Abstract: A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM), then etching a cut mask for a cPSM mask. Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning steps which form combined patterns through the use of partial image transfers into an intermediate hard mask prior to final wafer patterning. The intermediate and final hard mask materials are chosen to prevent image transfer into an underlying substrate or wafer prior to the final etch process.

Abstract translation: 图案化方法允许互补掩模版集合的单独转移。 在一个实施例中，例如，该方法包括蚀刻相移掩模（PSM），然后蚀刻用于cPSM掩模的切割掩模。 此外，解耦互补掩模图案转移方法包括两个单独的和去耦的掩模图案化步骤，其通过在最终的晶片图案化之前通过使用部分图像转移到中间硬掩模中形成组合图案。 选择中间和最终硬掩模材料以防止在最终蚀刻工艺之前图像转移到下面的基底或晶片中。

公开(公告)号：US06586160B2

公开(公告)日：2003-07-01

申请号：US09817408

申请日：2001-03-26

Applicant: Chung-Peng Ho ,  Bernard J. Roman ,  Chong-Cheng Fu

Inventor： Chung-Peng Ho ,  Bernard J. Roman ,  Chong-Cheng Fu

IPC: G03F720

CPC classification number: G03F7/70333 ,  G03F7/70358

Abstract: A resist layer (34) on a semiconductor wafer (20) is patterned by using a scanning exposure system (50) which provides light, containing pattern information which is intended to be transferred to the wafer. The lithographic system is a step and scan system in which a reticle (16) passes between a light source and a lens system(18). The wafer with the resist layer is passed through a focal plane of the patterned light at a tilt angle (&thgr;). The user selects a desirable range for the depth of the resist to be exposed at the focus of the patterned light. The tilt angle is calculated by taking the arc tangent of the desirable range divided by a width of a slit region (52) of the projected light. The depth of focus increases over standard step and scan techniques.

公开(公告)号：US06168904A

公开(公告)日：2001-01-02

申请号：US08939422

申请日：1997-09-29

Applicant: John David Cuthbert ,  Chong-Cheng Fu

Inventor： John David Cuthbert ,  Chong-Cheng Fu

IPC: G03C500

CPC classification number: G03F7/70466 ,  G03F7/203

Abstract: An improved method of integrated circuit fabrication is described with a photolithographic step involving pattern decomposition. A desired final pattern is decomposed into two or more component patterns for photoresist imaging, leading to improvements in image fidelity.

Abstract translation: 通过涉及图案分解的光刻步骤描述了集成电路制造的改进方法。 期望的最终图案被分解成用于光致抗蚀剂成像的两个或更多个组件图案，导致图像保真度的改善。

公开(公告)号：US4519260A

公开(公告)日：1985-05-28

申请号：US574065

申请日：1984-01-26

Applicant: Chong-Cheng Fu ,  Levy Gerzberg

Inventor： Chong-Cheng Fu ,  Levy Gerzberg

IPC: G01F1/66 ,  G01P5/24 ,  G10K11/26 ,  G10K11/34

CPC classification number: G10K11/348 ,  G01F1/662 ,  G01P5/24 ,  G10K11/26

Abstract: Transducer structures for use in volume flow measurements which generate a first uniform beam and a second focused beam within the uniform beam. The transducer may include concentric elements, a linear array, or combinations thereof. In a two element concentric array, a central disc generates a uniform beam and a peripheral annular element having a lens thereon defines a second focused beam within the first beam. In a linear array a plurality of juxtaposed linear elements define a scan surface and a segmented element within the linear element array defines a focused reference sample volume within the scanned surface. A concentric array having a plurality of annular elements is driven with amplitude weighting of each element in accordance with a Fourier-Bessel approximation to the desired beam pattern thereby electronically achieving ultrasonic beam width control.

Abstract translation: 用于体积流量测量的传感器结构，其在均匀波束内产生第一均匀波束和第二聚焦光束。 换能器可以包括同心元件，线性阵列或其组合。 在两元件同心圆盘阵列中，中心盘产生均匀的光束，并且具有透镜的外围环形元件在第一光束内限定第二聚焦光束。 在线性阵列中，多个并置的线性元件限定了扫描表面，线性元件阵列内的分段元件限定了扫描表面内的聚焦参考样本体积。 具有多个环形元件的同心圆盘阵列根据对期望的波束图案的傅立叶 - 贝塞尔近似来驱动每个元件的振幅加权，从而电子地实现超声波束宽度控制。

公开(公告)号：US20080085609A1

公开(公告)日：2008-04-10

申请号：US11461033

申请日：2006-07-31

Applicant: James E. Vasek ,  Nicole R. Ellis ,  Chong-Cheng Fu

Inventor： James E. Vasek ,  Nicole R. Ellis ,  Chong-Cheng Fu

IPC: H01L21/31

CPC classification number: H01L21/32139 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11539

Abstract: A method for protecting at least one high-topography region on a substrate having both the at least one high-topography region and the at least one low-topography region is provided. The method comprises patterning a thick photo-resist layer having a first thickness, such that the thick photo-resist layer is formed on at least a portion of only the at least one high-topography region, wherein the high-topography region comprises a plurality of semiconductor devices of a first type. The method further comprises patterning a thin photo-resist layer having a second thickness, wherein the first thickness is greater than the second thickness, such that the patterned thin photo-resist layer is formed on at least a portion of only the at least one low-topography region. The method further comprises forming a plurality of semiconductor devices of a second type in the at least the portion of the low-topography region. The method further comprises removing both the thick photo-resist layer and the thin photo-resist layer.

Abstract translation: 提供了一种用于保护具有至少一个高地形区域和至少一个低地形区域的基底上的至少一个高地形区域的方法。 该方法包括图案化具有第一厚度的厚的光致抗蚀剂层，使得厚的光致抗蚀剂层形成在仅至少一个高地形区域的至少一部分上，其中高地形区域包括多个 的第一类半导体器件。 该方法还包括对具有第二厚度的薄的光致抗蚀剂层进行图案化，其中第一厚度大于第二厚度，使得图案化的光致抗蚀剂层形成在至少一个低至少一个的至少一部分上 地形区域。 该方法还包括在低地形区域的至少一部分中形成第二类型的多个半导体器件。 该方法还包括去除厚的光致抗蚀剂层和薄的光致抗蚀剂层。

公开(公告)号：US5057462A

公开(公告)日：1991-10-15

申请号：US413356

申请日：1989-09-27

Applicant: Juli H. Eisenberg ,  Larry B. Fritzinger ,  Chong-Cheng Fu ,  Taeho Kook ,  Thomas M. Wolf

Inventor： Juli H. Eisenberg ,  Larry B. Fritzinger ,  Chong-Cheng Fu ,  Taeho Kook ,  Thomas M. Wolf

IPC: G03F1/08 ,  G03F7/20 ,  H01L21/027 ,  H01L21/30 ,  H01L21/302 ,  H01L21/3065

CPC classification number: G03F7/20 ,  Y10S438/941 ,  Y10S438/948

Abstract: In the manufacture of integrated-circuit devices, patterned features are made on a substrate by etching a deposited layer. The pattern comprises features which are closely spaced, as well as others which are more isolated. Etching is in approximate conformance with a lithographically defined resist pattern which in turn is in approximate conformance with a desired pattern. A processing parameter such as, e.g., resist layer thickness is chosen such that an etched pattern is obtained which approximates a desired pattern more closely than a lithographically defined resist pattern.

公开(公告)号：US20120007155A1

公开(公告)日：2012-01-12

申请号：US13235580

申请日：2011-09-19

Applicant: MARK D. HALL ,  Glenn C. Abeln ,  Chong-Cheng Fu

Inventor： MARK D. HALL ,  Glenn C. Abeln ,  Chong-Cheng Fu

IPC: H01L29/772

CPC classification number: H01L21/76232 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract translation: 在半导体层中和半导体层上实现制造半导体器件的方法。 在第一有效区域附近形成沟槽。 沟槽填充绝缘材料。 掩模特征形成在沟槽的中心部分上，以在掩蔽特征的第一侧和第一有效区域之间露出沟槽的第一侧。 蚀刻到沟槽的第一侧的步骤在沟槽中留下第一凹槽。 在第一凹槽中生长第一外延区域以使第一有源区域延伸以包括第一凹部，从而形成延伸的第一有源区域。