公开(公告)号：US20080237742A1

公开(公告)日：2008-10-02

申请号：US11694458

申请日：2007-03-30

Applicant: Pushkar Ranade ,  Keith Zawadzki ,  Christopher Auth

Inventor： Pushkar Ranade ,  Keith Zawadzki ,  Christopher Auth

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7848

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括等离子体蚀刻晶体管的源极/漏极区域的一部分，然后沿（100）面选择性地湿蚀刻源极漏极区域，以在凹陷源极/漏极区域中形成至少一个（111）区域。

公开(公告)号：US20080237741A1

公开(公告)日：2008-10-02

申请号：US11694418

申请日：2007-03-30

Applicant: Pushkar Ranade ,  Keith Zawadzki ,  Christopher Auth

Inventor： Pushkar Ranade ,  Keith Zawadzki ,  Christopher Auth

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括等离子体蚀刻晶体管的源极/漏极区域的一部分，然后沿（100）面选择性地湿蚀刻源极漏极区域，以在凹陷源极/漏极区域中形成至少一个（111）区域。

公开(公告)号：US20070034945A1

公开(公告)日：2007-02-15

申请号：US11586154

申请日：2006-10-24

Applicant: Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

Inventor： Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

IPC: H01L29/76

CPC classification number: H01L29/66628 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

Abstract: Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.

Abstract translation: PMOS晶体管的沟道区域中的最佳应变由硅合金材料在与衬底表面非平面关系的器件的接合区域中提供。 选择硅合金材料，硅合金材料的尺寸以及硅合金材料与基板表面的非平面关系，使得硅合金材料的晶格间距与 衬底在衬底表面以下以及衬底表面之上的硅合金材料中引起应变，以影响衬底通道中最佳的硅合金诱导应变。 此外，可以选择非平面关系，使得由在硅合金材料上形成的不同格子间隔层引起的任何应变对通道区域中的应变具有降低的影响。

公开(公告)号：US20080311720A1

公开(公告)日：2008-12-18

申请号：US12218157

申请日：2008-07-11

Applicant: Thomas Hoffman ,  Sunit Tyagi ,  Giuseppe Curello ,  Berhard Sell ,  Christopher Auth

Inventor： Thomas Hoffman ,  Sunit Tyagi ,  Giuseppe Curello ,  Berhard Sell ,  Christopher Auth

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of forming a transistor comprising: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.

Abstract translation: 一种形成晶体管的方法，包括：在其源极/漏极区域处在衬底中限定底切凹部，在栅电极下方延伸的底切凹部; 在所述凹部之间的所述栅极电极下面形成晕圈植入区域; 并且在产生晕圈植入区域之后在底切凹槽中提供升高的源极/漏极结构。

公开(公告)号：US20080237603A1

公开(公告)日：2008-10-02

申请号：US11693608

申请日：2007-03-29

Applicant: Saurabh Lodha ,  Pushkar Ranade ,  Christopher Auth

Inventor： Saurabh Lodha ,  Pushkar Ranade ,  Christopher Auth

IPC: H01L21/8238

CPC classification number: H01L21/26506 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/665 ,  H01L29/7833 ,  Y10T29/49121 ,  Y10T29/49147 ,  Y10T29/49156

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, and annealing the at least one contact area to form at least one silicide.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括通过至少一个接触开口注入晶体管结构的源极/漏极区域的至少一个接触区域，在至少一个接触区域上形成第一金属层，形成第二层金属 所述第一金属层选择性地蚀刻所述第二金属层的一部分，以及退火所述至少一个接触区域以形成至少一个硅化物。

公开(公告)号：US07861406B2

公开(公告)日：2011-01-04

申请号：US11693608

申请日：2007-03-29

Applicant: Saurabh Lodha ,  Pushkar Ranade ,  Christopher Auth

Inventor： Saurabh Lodha ,  Pushkar Ranade ,  Christopher Auth

IPC: H01R43/00

CPC classification number: H01L21/26506 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/665 ,  H01L29/7833 ,  Y10T29/49121 ,  Y10T29/49147 ,  Y10T29/49156

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, annealing the at least one contact area to form at least one silicide, and removing the unreacted first metal layer and second metal layer from the transistor structure and forming a conductive material in the at least one contact opening.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括通过至少一个接触开口注入晶体管结构的源极/漏极区域的至少一个接触区域，在至少一个接触区域上形成第一金属层，形成第二层金属 所述第一金属层选择性蚀刻所述第二金属层的一部分，退火所述至少一个接触区域以形成至少一个硅化物，以及从所述晶体管结构去除所述未反应的第一金属层和第二金属层并形成导电材料 在所述至少一个接触开口中。

公开(公告)号：US07691752B2

公开(公告)日：2010-04-06

申请号：US11694458

申请日：2007-03-30

Applicant: Pushkar Ranade ,  Keith Zawadzki ,  Christopher Auth

Inventor： Pushkar Ranade ,  Keith Zawadzki ,  Christopher Auth

IPC: H01L21/31 ,  H01L21/469 ,  H01L29/04

CPC classification number: H01L29/66636 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7848

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括等离子体蚀刻晶体管的源极/漏极区域的一部分，然后沿（100）面选择性地湿蚀刻源极漏极区域，以在凹陷源极/漏极区域中形成至少一个（111）区域。

公开(公告)号：US20060065937A1

公开(公告)日：2006-03-30

申请号：US10954914

申请日：2004-09-30

Applicant: Thomas Hoffmann ,  Sunit Tyagi ,  Giuseppe Curello ,  Berhard Sell ,  Christopher Auth

Inventor： Thomas Hoffmann ,  Sunit Tyagi ,  Giuseppe Curello ,  Berhard Sell ,  Christopher Auth

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.

Abstract translation: 在其上具有栅电极并限定源/漏区的MOS器件的衬底中提供卤素注入区的方法，根据上述方法制造的MOS器件和包括MOS器件的系统。 该方法包括：在其源极/漏极区域处限定衬底中的底切凹部，在栅电极下方延伸的底切凹部; 在所述凹部之间的所述栅极电极下面形成晕圈植入区域; 并且在产生晕圈植入区域之后在底切凹槽中提供升高的源极/漏极结构。

公开(公告)号：US20050104057A1

公开(公告)日：2005-05-19

申请号：US11024259

申请日：2004-12-27

Applicant: M. Shaheed ,  Thomas Hoffmann ,  Mark Armstrong ,  Christopher Auth

Inventor： M. Shaheed ,  Thomas Hoffmann ,  Mark Armstrong ,  Christopher Auth

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66636 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7843

Abstract: An intentional recess or indentation is created in a region of semiconductor material that will become part of a channel of a metal oxide semiconductor (MOS) transistor structure. A layer is created on a surface of the recess to induce an appropriate type of stress in the channel.

Abstract translation: 在将成为金属氧化物半导体（MOS）晶体管结构的沟道的一部分的半导体材料的区域中产生有意的凹陷或凹陷。 在凹槽的表面上产生一层以在通道中引起适当类型的应力。