-
公开(公告)号：US08619762B2
公开(公告)日：2013-12-31
申请号：US12147326
申请日：2008-06-26
Applicant: ChulKyu Lee , George Alan Wiley
Inventor： ChulKyu Lee , George Alan Wiley
Abstract: A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit streams. The first and second bit streams are respectively serially shifted along a first plurality of shift registers and a second plurality of shift registers. A first portion of the first bit stream in the first plurality of shift registers is selected and a second portion of the second bit stream in the second plurality of shift registers is also selected. A parallel group of data in a parallel data stream is formed from the first and second portions.
Abstract translation: 解串器电路和方法根据并行分组将串行比特流转换成并行比特流。 解串器和方法包括将串行数据流交替解复用为第一和第二位流。 第一和第二比特流分别沿着第一多个移位寄存器和第二多个移位寄存器串行移位。 选择第一多个移位寄存器中的第一比特流的第一部分，并且还选择第二多个移位寄存器中的第二比特流的第二部分。 并行数据流中的并行数据组由第一和第二部分形成。
-
公开(公告)号：US20130205890A1
公开(公告)日：2013-08-15
申请号：US13703090
申请日：2010-08-23
Applicant: Jae-Won Jung , Ki-Ho Chang , Jin-Young Bae , Chulkyu Lee , Gyuwon Lee , Young-Jean Choi
Inventor： Jae-Won Jung , Ki-Ho Chang , Jin-Young Bae , Chulkyu Lee , Gyuwon Lee , Young-Jean Choi
CPC classification number: G01B11/02 , G01N9/04 , G01N15/0205 , G01N2015/0294 , G01N2015/1075 , G01N2015/1497 , G01W1/14
Abstract: Provided is a disdrometer system having a three-dimensional laser array unit, including: a plurality of laser transmitting parts which are arranged on an inner side of a cylindrical body to generate a laser beam; a plurality of laser receiving parts which are arranged on the inner side of the cylindrical body to correspond to the laser transmitting parts; and a laser control part which converts a cut-off signal of the laser beam, which is cut-off by precipitation drops flowing into the inner side of the cylindrical body, into an electrical signal, and records the converted electrical signal. Thus, the disdrometer system has an effect that the shape, volume, number, falling velocity of precipitation drops, and the intensity, density and weight of rainfall can be integrally measured.
Abstract translation: 本发明提供一种具有三维激光阵列单元的曝光器系统，包括：多个激光透射部件，其布置在圆柱体的内侧以产生激光束; 多个激光接收部，其配置在与所述激光传送部对应的所述圆筒体的内侧; 以及激光控制部，其将通过流入圆筒体的内侧的析出滴下的激光束的截止信号转换为电信号，并记录转换后的电信号。 因此，降温系统具有能够整体测量降水的形状，体积，数量，降水速度，降雨强度，密度和重量等的影响。
-
公开(公告)号：US08405426B2
公开(公告)日：2013-03-26
申请号：US12789566
申请日：2010-05-28
Applicant: Chulkyu Lee , Harry H. Dang , Abhay S. Dixit
Inventor： Chulkyu Lee , Harry H. Dang , Abhay S. Dixit
IPC: H03K19/00
CPC classification number: H03K19/096 , G06F17/50 , H03K19/20 , H03M9/00
Abstract: A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a selection circuit, where the input tier includes multiple combinatorial gate multiplexers. The method further includes selecting an output value at an output tier of the selection circuit, where the output tier includes at least one combinatorial gate multiplexer.
Abstract translation: 公开了串行化并行数据输入值的方法和装置。 在特定实施例中，串行化并行数据输入值的方法包括在选择电路的输入层并行地接收多个数据输入值，其中输入层包括多个组合门多路复用器。 所述方法还包括在所述选择电路的输出层选择输出值，其中所述输出层包括至少一个组合门多路复用器。
-
公开(公告)号：US20090002027A1
公开(公告)日：2009-01-01
申请号：US11768300
申请日：2007-06-26
Applicant: ChulKyu Lee
Inventor： ChulKyu Lee
IPC: H03K19/0175
CPC classification number: H03K3/356113
Abstract: A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal onto a first input of the level shifting latch and supplies an inverted version of the input signal onto a second input of the level shifting latch. A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.
Abstract translation: 电平移位器包括反相电路，交叉耦合电平移位锁存器和SR逻辑门锁存器。 电平移位锁存器的第一和第二输出耦合到SR锁存器的组（S）和复位（R）输入端。 由第一电源电压VDDL供电的反相电路将输入信号的非反相版本提供到电平移位锁存器的第一输入端，并将输入信号的反相版本提供给电平移位锁存器的第二输入。 输入信号的低电平到高电平跳变使SR锁存器复位，而高电平至低电平转换则设置SR锁存器。 电平转换器的占空比失真偏移在电压，过程和温度转角上小于50皮秒，电平转换器的电源电压裕度大于VDDL额定值的四分之一。
-
5.发明申请SERIALIZER AND DESERIALIZER FOR ODD RATIO PARALLEL DATA BUS 有权用于ODD比例并行数据总线的SERIALIZER和DESERIALIZER公开(公告)号：US20170060218A1
公开(公告)日：2017-03-02
申请号：US15302767
申请日：2014-05-21
Applicant: Wenjen SU , Le ZHANG , Chulkyu LEE , QUALCOMM Incorporated
Inventor： Le Zhang , Wenjun Su , Chulkyu Lee
CPC classification number: G06F1/324 , G06F1/08 , G06F13/4022 , G06F13/4282 , G11C19/28 , H03M9/00 , Y02D10/14 , Y02D10/151
Abstract: Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.
Abstract translation: 公开了用于奇数比并行数据总线的串行器和解串器。 在一个实施例中，以奇数个并行数据位操作的串行器和解串行器与半速率时钟一起工作，以全时钟速率提供串行数据流。 通过提供半速率时钟，集成了串行器的集成电路的功率和面积是保守的。 此外，通过提供7：1串行器，该总线现在与MIPI C-PHY标准兼容。
-
Patent Agency Ranking
公开(公告)号：US20110291703A1
公开(公告)日：2011-12-01
申请号：US12789566
申请日：2010-05-28
Applicant: Chulkyu Lee , Harry H. Dang , Abhay S. Dixit
Inventor： Chulkyu Lee , Harry H. Dang , Abhay S. Dixit
IPC: H03K19/096 , G06F17/50 , H03K19/20
CPC classification number: H03K19/096 , G06F17/50 , H03K19/20 , H03M9/00
Abstract: A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a selection circuit, where the input tier includes multiple combinatorial gate multiplexers. The method further includes selecting an output value at an output tier of the selection circuit, where the output tier includes at least one combinatorial gate multiplexer.
Abstract translation: 公开了串行化并行数据输入值的方法和装置。 在特定实施例中，串行化并行数据输入值的方法包括在选择电路的输入层处并行地接收多个数据输入值，其中输入层包括多个组合门多路复用器。 该方法还包括在选择电路的输出层选择输出值，其中输出层包括至少一个组合门多路复用器。
-
公开(公告)号：US08746056B2
公开(公告)日：2014-06-10
申请号：US13703090
申请日：2010-08-23
Applicant: Jae-Won Jung , Ki-Ho Chang , Jin-Young Bae , Chulkyu Lee , Gyuwon Lee , Young Jean Choi
Inventor： Jae-Won Jung , Ki-Ho Chang , Jin-Young Bae , Chulkyu Lee , Gyuwon Lee , Young Jean Choi
IPC: G01W1/00
CPC classification number: G01B11/02 , G01N9/04 , G01N15/0205 , G01N2015/0294 , G01N2015/1075 , G01N2015/1497 , G01W1/14
Abstract: Provided is a disdrometer system having a three-dimensional laser array unit, including: a plurality of laser transmitting parts which are arranged on an inner side of a cylindrical body to generate a laser beam; a plurality of laser receiving parts which are arranged on the inner side of the cylindrical body to correspond to the laser transmitting parts; and a laser control part which converts a cut-off signal of the laser beam, which is cut-off by precipitation drops flowing into the inner side of the cylindrical body, into an electrical signal, and records the converted electrical signal. Thus, the disdrometer system has an effect that the shape, volume, number, falling velocity of precipitation drops, and the intensity, density and weight of rainfall can be integrally measured.
Abstract translation: 本发明提供一种具有三维激光阵列单元的曝光器系统，包括：多个激光透射部件，其布置在圆柱体的内侧以产生激光束; 多个激光接收部，其配置在与所述激光传送部对应的所述圆筒体的内侧; 以及激光控制部，其将通过流入圆筒体的内侧的析出滴下的激光束的截止信号转换为电信号，并记录转换后的电信号。 因此，降温系统具有能够整体测量降水的形状，体积，数量，降水速度，降雨强度，密度和重量等的影响。
-
公开(公告)号：US07956642B2
公开(公告)日：2011-06-07
申请号：US11768300
申请日：2007-06-26
Applicant: ChulKyu Lee
Inventor： ChulKyu Lee
IPC: H03K19/094 , H03L5/00
CPC classification number: H03K3/356113
Abstract: A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal onto a first input of the level shifting latch and supplies an inverted version of the input signal onto a second input of the level shifting latch. A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.
Abstract translation: 电平移位器包括反相电路，交叉耦合电平移位锁存器和SR逻辑门锁存器。 电平移位锁存器的第一和第二输出耦合到SR锁存器的组（S）和复位（R）输入端。 由第一电源电压VDDL供电的反相电路将输入信号的非反相版本提供到电平移位锁存器的第一输入端，并将输入信号的反相版本提供给电平移位锁存器的第二输入。 输入信号的低电平到高电平跳变使SR锁存器复位，而高电平至低电平转换则设置SR锁存器。 电平转换器的占空比失真偏移在电压，过程和温度转角上小于50皮秒，电平转换器的电源电压裕度大于VDDL额定值的四分之一。
-
公开(公告)号：US20090323731A1
公开(公告)日：2009-12-31
申请号：US12147326
申请日：2008-06-26
Applicant: ChulKyu Lee , George Alan Wiley
Inventor： ChulKyu Lee , George Alan Wiley
IPC: H04J3/04
Abstract: A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit streams. The first and second bit streams are respectively serially shifted along a first plurality of shift registers and a second plurality of shift registers. A first portion of the first bit stream in the first plurality of shift registers is selected and a second portion of the second bit stream in the second plurality of shift registers is also selected. A parallel group of data in a parallel data stream is formed from the first and second portions.
Abstract translation: 解串器电路和方法根据并行分组将串行比特流转换成并行比特流。 解串器和方法包括将串行数据流交替解复用为第一和第二位流。 第一和第二比特流分别沿着第一多个移位寄存器和第二多个移位寄存器串行移位。 选择第一多个移位寄存器中的第一比特流的第一部分，并且还选择第二多个移位寄存器中的第二比特流的第二部分。 并行数据流中的并行数据组由第一和第二部分形成。
-
公开(公告)号：US20090225873A1
公开(公告)日：2009-09-10
申请号：US12042362
申请日：2008-03-05
Applicant: Chulkyu Lee , Anosh Davierwalla , George Wiley
Inventor： Chulkyu Lee , Anosh Davierwalla , George Wiley
IPC: H04B3/00
CPC classification number: H04L25/0272 , H04L25/49
Abstract: Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.
Abstract translation: 公开了数据传输的系统和方法。 在一个实施例中，选择性地激活至少两个发射机，并且至少一个发射机在串行接口处被去激活，以经由至少两条不同的线路传输数据。
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.014 seconds)
