公开(公告)号：US06350671B1

公开(公告)日：2002-02-26

申请号：US09579778

申请日：2000-05-26

Applicant: Claudio Brambilla ,  Manlio Sergio Cereda ,  Paolo Caprara

Inventor： Claudio Brambilla ,  Manlio Sergio Cereda ,  Paolo Caprara

IPC: H01L214263

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76885 ,  H01L2924/3011

Abstract: A method for autoaligning lines of a conductive material in circuits integrated on a semiconductor substrate is presented. The method includes forming several regions projecting from the substrate surface and aligned to one another, and forming a fill layer in the gaps between the projecting regions. The fill layer is planarized to expose the regions, and a portion of the regions is removed to form holes at the locations of the regions. Next an insulating layer is formed in the holes. The insulating layer is selectively removed to form spacers along the edges of said holes and at least one conductive layer is deposited over the exposed surface. Later, a step of photolithograpy with a mask is performed and the conductive layer is etched to define lines and collimate them to the underlying regions.

Abstract translation: 提出了一种在集成在半导体衬底上的电路中自动对准导电材料线的方法。 该方法包括形成从基板表面突出并且彼此对准的若干区域，并且在突出区域之间的间隙中形成填充层。 将填充层平坦化以暴露区域，并且去除部分区域以在区域的位置处形成孔。 接下来，在孔中形成绝缘层。 选择性地去除绝缘层以沿着所述孔的边缘形成间隔物，并且至少一个导电层沉积在暴露的表面上。 之后，进行用掩模进行光刻的步骤，蚀刻导电层以限定线并将它们准直到下面的区域。

公开(公告)号：US06326266B1

公开(公告)日：2001-12-04

申请号：US09141849

申请日：1998-08-27

Applicant: Claudio Brambilla ,  Valerio Cassio ,  Paolo Caprara ,  Manlio Sergio Creda

Inventor： Claudio Brambilla ,  Valerio Cassio ,  Paolo Caprara ,  Manlio Sergio Creda

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A method of manufacturing a semiconductor virtual ground memory device having a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel stripes. The device also includes a circuit portion for selection transistors and decode and address circuit portions having P-channel and N-channel MOS transistors. According to the method, N-wells are formed in at least one substrate portion to accommodate the P-channel transistors, active areas of all transistors are defined using a screening mask, and then an isolation layer is grown through the apertures of the screening mask. The screening mask is not open over the matrix region of the memory cells.

Abstract translation: 一种半导体虚拟接地存储器件的制造方法，该半导体虚拟接地存储器件具有形成在半导体衬底上的浮置栅极存储器单元的矩阵，该多个连续位线跨越衬底延伸为离散的平行条纹。 该器件还包括用于选择晶体管的电路部分，以及具有P沟道和N沟道MOS晶体管的解码和寻址电路部分。 根据该方法，在至少一个衬底部分中形成N阱以容纳P沟道晶体管，使用屏蔽掩模限定所有晶体管的有源区，然后通过掩模掩模的孔生长隔离层 。 筛选掩模在存储单元的矩阵区域上不开放。

公开(公告)号：US06353243B1

公开(公告)日：2002-03-05

申请号：US09356080

申请日：1999-07-16

Applicant: Claudio Brambilla ,  Manlio Sergio Cereda ,  Giancarlo Ginami

Inventor： Claudio Brambilla ,  Manlio Sergio Cereda ,  Giancarlo Ginami

IPC: H01L2348

CPC classification number: H01L27/11526 ,  H01L23/5283 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11543 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD), said defining the second strips (17) providing for selectively etching the first and second layers of conductive material (9,11) outside the memory cell array area by means of a first mask (MASK1), and said defining the first strips (22) providing for selectively etching the second layer of conductive material (11), the layer of insulating material (10) and the first layer of conductive material (9) inside the memory cell array area by means of a second mask (MASK2).

Abstract translation: 一种用于制造集成电路的方法，该集成电路包括存储单元阵列，提供：a）在半导体层（6）的存储单元阵列区域中形成用于存储单元的有效区域; b）在所述存储单元的所述有源区上形成栅极氧化物层（8）; c）在整个集成电路上形成第一层导电材料（9）; d）在第一层导电材料（9）上形成一层绝缘材料（10）; e）从存储单元阵列区域的外部去除绝缘材料层（10）; f）在整个集成电路上形成第二层导电材料（11），其在存储单元阵列区域中通过绝缘材料层（10）与第一导电材料层（9）分离，而在存储单元外部 阵列区域直接叠加在所述第一导电材料层（9）上; g）在存储单元阵列区域内部，限定用于形成存储单元阵列（1）的行（3）的第二导电材料层（11）的第一条带（22），以及限定第二条带 用于形成用于将存储单元阵列的行（3）与电路（5，RD）电互连的互连线（100）的第二层导电材料（11）的第二层（17），所述第二层导电材料（11） 提供通过第一掩模（MASK1）选择性地蚀刻存储单元阵列区域外的第一和第二导电材料层（9,11），并且所述第一条带（22）限定第二条带 导电材料（11），绝缘材料层（10）和第一层导电材料（9）通过第二掩模（MASK2）在存储单元阵列区域内。

公开(公告)号：US07115472B2

公开(公告)日：2006-10-03

申请号：US10964049

申请日：2004-10-12

Applicant: Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda

Inventor： Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda

IPC: H01L21/8242

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923

Abstract: A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

公开(公告)号：US06825523B2

公开(公告)日：2004-11-30

申请号：US10267033

申请日：2002-10-07

Applicant: Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda

Inventor： Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda

IPC: H01L2976

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923

Abstract: A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

Abstract translation: 一种用于制造双电荷存储位置电可编程存储单元的方法，包括在半导体衬底上形成中心绝缘栅极的步骤; 形成物理上分离的电荷限制层，堆叠在中心栅极侧的介质电荷捕获材料 - 电介质层堆叠部分，每个电荷限制层堆叠部分中的电荷捕获材料层形成电荷存储元件; 在每个电荷限制层堆叠部分上形成侧面控制栅极; 在侧控制门侧面形成存储单元源极/漏极区; 并将侧面控制门电连接到中央门。 在中心栅极侧面的电荷限制层堆叠部分中的每一个形成为“L”形，基底电荷限制层堆叠部分位于衬底表面上，并且垂直电荷限制层堆叠部分抵靠 绝缘门的相应侧。

公开(公告)号：US06365456B1

公开(公告)日：2002-04-02

申请号：US09507777

申请日：2000-02-18

Applicant: Manlio Sergio Cereda ,  Claudio Brambilla ,  Paolo Caprara

Inventor： Manlio Sergio Cereda ,  Claudio Brambilla ,  Paolo Caprara

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L21/0337 ,  H01L29/66825

Abstract: A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells is presented. In the memory device, the matrix is formed on a semiconductor substrate with a number of continuous bit lines extending across the substrate as discrete parallel strips. The process begins by growing an oxide layer over the matrix region and depositing over the semiconductor throughout a stack structure which comprises a first conductor layer, a first dielectric layer, and a second conductor layer. Then a second dielectric layer is deposited over the stack structure, and floating gate regions are defined by photolithography using a mask of “POLY1 along a first direction”, to thereby define in the dielectric layer, a plurality of parallel strips which delimit a first dimension of floating gate regions. Next the dielectric layer is etched away to define a plurality of parallel dielectric strips and a number of dielectric islands are defined by photolithography using a mask of “POLY1 along a second direction” in the plurality of parallel strips. The dielectric layer is etched to define the plurality of islands. Finally, the stack structure and the thin gate oxide layer are etched to define gate regions of the matrix cells using said oxide island.

Abstract translation: 本发明提供一种制造具有虚拟接地并且至少包括浮动栅极存储单元矩阵的电子半导体集成存储器件的工艺。 在存储器件中，矩阵形成在半导体衬底上，多个连续的位线作为离散的平行条延伸穿过衬底。 该过程开始于在矩阵区域上生长氧化物层并且在包括第一导体层，第一介电层和第二导体层的整个堆叠结构中沉积在半导体上。 然后在堆叠结构上沉积第二介电层，并且通过使用“POLY1沿着第一方向”的掩模的光刻法定义浮动栅极区域，从而在电介质层中限定多个平行的条，其限定第一维度 的浮动门区域。 接下来，蚀刻掉电介质层以限定多个平行的介质条，并且通过使用在多个平行条带中的沿着第二方向的“POLY1”的掩模的光刻来限定多个介电岛。 蚀刻介电层以限定多个岛。 最后，使用所述氧化物岛蚀刻所述堆叠结构和所述薄栅极氧化物层以限定所述矩阵单元的栅极区域。

公开(公告)号：US06300195B1

公开(公告)日：2001-10-09

申请号：US09512900

申请日：2000-02-25

Applicant: Pierantonio Pozzoni ,  Claudio Brambilla ,  Sergio Cereda ,  Paolo Caprara ,  Rustom Irani

Inventor： Pierantonio Pozzoni ,  Claudio Brambilla ,  Sergio Cereda ,  Paolo Caprara ,  Rustom Irani

IPC: H01L21336

CPC classification number: H01L27/11521

Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and including at least a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips begins with forming an oxide layer over the matrix region. Then, the semiconductor throughout is deposited with a stack structure which includes a first conductor layer, a first dielectric layer, and second conductor layer. Next, a second dielectric layer is formed. Floating gate regions are defined by photolithography using a mask of “POLY1 along a first predetermined direction”, and associated etching, to define, in the stack structure, a plurality of parallel openings. These openings are implanted to confer a predetermined conductivity on the bit line regions. Next, the parallel openings are filled with a photo-sensitive material to protect the matrix bit lines.

Abstract translation: 一种用于制造具有虚拟接地并且至少包括形成在半导体衬底上的浮动栅极存储器单元的矩阵的电子半导体集成电子存储器件的工艺，其具有跨越衬底延伸的多个连续位线作为离散的平行条带，开始形成氧化物层 超过矩阵区域。 然后，整个半导体层叠有包括第一导体层，第一介电层和第二导体层的堆叠结构。 接下来，形成第二电介质层。 通过使用“沿着第一预定方向的”POLY1“掩模的光刻法和相关联的蚀刻来限定浮动栅极区域，以在堆叠结构中限定多个平行的开口。 植入这些开口以赋予位线区域上预定的导电性。 接下来，平行的开口填充有光敏材料以保护矩阵位线。

公开(公告)号：US06251736B1

公开(公告)日：2001-06-26

申请号：US09473368

申请日：1999-12-28

Applicant: Claudio Brambilla ,  Sergio Manlio Cereda ,  Paolo Caprara

Inventor： Claudio Brambilla ,  Sergio Manlio Cereda ,  Paolo Caprara

IPC: H01L21336

CPC classification number: H01L27/11521 ,  Y10S438/976

Abstract: A process for manufacturing a MOS transistor and especially a MOS transistor used for non-volatile memory cells is presented. At the start of the manufacturing, a semiconductor substrate having a first type of conductivity is covered by a gate oxide layer. A gate electrode is formed over the gate oxide layer, which is a stacked gate when the MOS transistor is used in a non-volatile memory. Covering the gate electrode is a covering oxide that is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next, a dopant of a second type of conductivity is implanted to provide implant regions adjacent to the gate electrode. Subjecting the semiconductor to thermal treatments allows the implanted regions to diffuse into the semiconductor substrate under the gate electrode and form a gradual junction drain and source region of the MOS transistor.

Abstract translation: 本发明提供一种制造用于非易失性存储单元的MOS晶体管，特别是MOS晶体管的工艺。 在制造开始时，具有第一类导电性的半导体衬底被栅极氧化物层覆盖。 在MOS晶体管用于非易失性存储器中的栅极氧化物层上形成栅电极，栅极氧化层是层叠栅极。 覆盖栅电极是在栅极氧化物层，栅电极和栅电极周围形成的覆盖氧化物。 接下来，注入第二类导电性的掺杂剂以提供邻近栅电极的注入区。 使半导体进行热处理允许注入区域扩散到栅电极下方的半导体衬底中，并形成MOS晶体管的逐渐连接漏极和源极区域。

公开(公告)号：US6104058A

公开(公告)日：2000-08-15

申请号：US898155

申请日：1997-07-22

Applicant: Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

Inventor： Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.

Abstract translation: 一种用于改善中间介质轮廓的方法，特别是用于由多个单元构成的非易失性存储器，包括以下步骤：在衬底上形成场氧化物区域和漏极活性区域区域; 在场氧化物区域上形成字线; 沉积氧化物以形成与字线相邻的氧化物翼; 通过掩蔽来源区域和漏极有源区域区域，保持在抗蚀剂覆盖的存储器内部的一个存储单元与另一个存储单元分离的场氧化物区域; 并且去除源区域中的场氧化物并从字线的两侧去除氧化物翼。

公开(公告)号：US5976933A

公开(公告)日：1999-11-02

申请号：US897799

申请日：1997-07-21

Applicant: Claudio Brambilla ,  Manlio Sergio Cereda ,  Giancarlo Ginami

Inventor： Claudio Brambilla ,  Manlio Sergio Cereda ,  Giancarlo Ginami

IPC: H01L21/8247 ,  H01L23/528 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L23/5283 ,  H01L27/115 ,  H01L27/11543 ,  H01L27/105 ,  H01L2924/0002

Abstract: A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD) said, first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.

Abstract translation: 一种用于制造集成电路的方法，该集成电路包括存储单元阵列，提供：a）在半导体层（6）的存储单元阵列区域中形成用于存储单元的有效区域; b）在所述存储单元的所述有源区上形成栅极氧化物层（8）; c）在整个集成电路上形成第一层导电材料（9）; d）在第一层导电材料（9）上形成一层绝缘材料（10）; e）从存储单元阵列区域的外部去除绝缘材料层（10）; f）在整个集成电路上形成第二层导电材料（11），其在存储单元阵列区域中通过绝缘材料层（10）与第一导电材料层（9）分离，而在存储单元外部 阵列区域直接叠加在所述第一导电材料层（9）上; g）在存储单元阵列区域内部，限定用于形成存储单元阵列（1）的行（3）的第二导电材料层（11）的第一条带（22），以及限定第二条带 用于形成用于将存储单元阵列的行（3）与电路（5，RD）电互连的互连线（100）的第二导电材料层（11）的第一层（17），所述第一条带（22）和 第二导电材料层（11）的第二条带（17）在其边界区域的各自端部自动连接。