公开(公告)号：US07263154B2

公开(公告)日：2007-08-28

申请号：US10680636

申请日：2003-10-07

Applicant: Tse-Hsiang Hsu ,  Ding-Jen Liu ,  Jong-Woei Chen ,  Chih-Cheng Chen

Inventor： Tse-Hsiang Hsu ,  Ding-Jen Liu ,  Jong-Woei Chen ,  Chih-Cheng Chen

IPC: H03D1/24 ,  H03L7/06

CPC classification number: G11B20/10009 ,  G11B27/3027 ,  G11B2220/216 ,  G11B2220/2575 ,  H03L7/081 ,  H03L7/10

Abstract: In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.

Abstract translation: 在用于在锁相环中实现快速时钟相位锁定的方法和装置中，采样时钟发生器响应于锁相环的振荡器输出产生采样时钟信号。 检测器单元在采样时钟信号的时钟边沿将输入数字信号采样到锁相环，以获得输入数字信号的多个采样点，并且比较每个时间上相邻的采样点对的逻辑电平，以检测 输入数字信号中的逻辑电平转换。 选择器单元由检测器单元控制，以选择一个采样时钟信号，其中一个采样时钟信号的时钟边沿之一限定了被检测为在输入数字信号中出现逻辑电平转换的间隔，随后 提供给锁相环作为输入锁相时钟信号。

公开(公告)号：US5517448A

公开(公告)日：1996-05-14

申请号：US303679

申请日：1994-09-09

Applicant: Ding-Jen Liu

Inventor： Ding-Jen Liu

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/0491

Abstract: A bias circuit for virtual ground non-volatile memory array with bank selector, utilizes static pull-up transistors connected respectively to all bit lines of the memory array. The gates of the static pull-up transistors are connected to a predetermined reference voltage for supplying a global bias voltage to the bit lines. Another predetermined reference voltage, acting as a local bias voltage, is supplied to a deselected virtual ground bit line which is adjacent to the selected data sense bit line. By these two bias techniques, the leakage current of the adjacent deselected "ON" memory cells is minimized; as a result, the stability of the current detector is largely enhanced; the probability of erroneous data reading is reduced; the operating voltage margin of the memory devices is enlarged; and the data accessing is expedited.

Abstract translation: 用于具有存储体选择器的虚拟接地非易失性存储器阵列的偏置电路使用分别连接到存储器阵列的所有位线的静态上拉晶体管。 静态上拉晶体管的栅极连接到用于向位线提供全局偏置电压的预定参考电压。 作为局部偏置电压的另一预定参考电压被提供给与所选择的数据检测位线相邻的取消选择的虚拟接地位线。 通过这两种偏置技术，相邻的取消选择的“ON”存储单元的漏电流最小化; 结果，电流检测器的稳定性大大提高; 数据读取错误的概率降低; 存储器件的工作电压裕度被扩大; 并加快了数据访问。

公开(公告)号：US5396467A

公开(公告)日：1995-03-07

申请号：US220248

申请日：1994-03-30

Applicant: Ding-Jen Liu ,  Jyh-Jen Cho

Inventor： Ding-Jen Liu ,  Jyh-Jen Cho

IPC: G11C7/06 ,  G11C16/28 ,  G11C7/00

CPC classification number: G11C7/062 ,  G11C16/28

Abstract: A two-phase sense amplifier includes a data sensing circuitry including a presetting current detecting circuit for allowing the sense amplifier to be in a presetting phase when an X-decoder decodes an address of a selected word line of a selected memory cell and a Y-decoder decodes an address of a selected bit line of the selected memory cell and then for setting a voltage level of the selected bit line to be around a switching point and an evaluating current detecting circuit for allowing the sense amplifier to be in an evaluating phase after the voltage level of the selected bit line is around the switching point in order to sense a current in the selected cell for converting the current into a voltage output, a dummy cell circuitry electrically connected to the data sensing circuitry for providing a reference voltage to the data sensing circuitry, and a differential amplifier electrically connected to the data sensing circuitry and the dummy cell circuitry for accepting and comparing the voltage output and the reference voltage to sense data of the selected memory cell. Such a sense amplifier can have a relatively high sensing speed.

Abstract translation: 一个双相位读出放大器包括一个数据检测电路，包括一个预置电流检测电路，用于当X解码器解码所选择的存储单元的选定字线的地址时，允许读出放大器处于预设阶段， 解码器对所选存储单元的所选位线的地址进行解码，然后将所选位线的电压电平设置在开关点周围，以及评估电流检测电路，用于允许读出放大器处于评估阶段 所选位线的电压电平在开关点周围，以便检测所选择的单元中的电流以将电流转换成电压输出;电连接到数据感测电路的虚设单元电路，用于向基准电压提供参考电压 数据感测电路和电连接到数据感测电路的差分放大器和用于接受和比较的虚拟单元电路 g电压输出和参考电压以检测所选存储单元的数据。 这种感测放大器可以具有相对高的感测速度。

公开(公告)号：US5317218A

公开(公告)日：1994-05-31

申请号：US46665

申请日：1993-04-12

Applicant: Ding-Jen Liu

Inventor： Ding-Jen Liu

IPC: G01R19/00

CPC classification number: G01R19/0092

Abstract: A current sense circuit with fast response for sensing a current input from a current source such as a memory cell, comprising a first amplifying means and a second amplifying means coupled to a first transistor and a second transistor, respectively. The first transistor is smaller in size than the second transistor and the reference voltage of the first amplifying means is slightly larger than the reference voltage of the second amplifying means. A load is coupled to the drain of the first transistor.

Abstract translation: 一种用于感测来自诸如存储单元的电流源的电流输入的具有快速响应的电流检测电路，包括分别耦合到第一晶体管和第二晶体管的第一放大装置和第二放大装置。 第一晶体管的尺寸小于第二晶体管，并且第一放大装置的参考电压略大于第二放大装置的参考电压。 负载耦合到第一晶体管的漏极。

公开(公告)号：US07242652B2

公开(公告)日：2007-07-10

申请号：US10285944

申请日：2002-10-31

Applicant: Chih-Cheng Chen ,  Ding-Jen Liu ,  Shun-Fang Tsai ,  Ming-Yang Chau

Inventor： Chih-Cheng Chen ,  Ding-Jen Liu ,  Shun-Fang Tsai ,  Ming-Yang Chau

IPC: G11B7/125

CPC classification number: G11B7/1263 ,  G11B7/00458

Abstract: An optical recording system includes a laser light source that provides an incident recording light signal for recording information on an optical recording medium, an optical detector for detecting a reflected write pulse from the optical recording medium, and a light source controller for controlling recording laser beam power of the laser light source according to a mark formation effectiveness signal generated by a signal generating device. The signal generating device includes an analog peak value detector for detecting a peak value of the reflected write pulse from the optical detector, at least one sample-hold circuit for sampling the reflected write pulse to obtain at least one amplitude value, and a processor for generating the mark formation effectiveness signal according to the peak value and the amplitude value.

Abstract translation: 一种光学记录系统，包括提供用于在光学记录介质上记录信息的入射记录光信号的激光源，用于检测来自光学记录介质的反射写入脉冲的光学检测器，以及用于控制记录激光束 根据由信号发生装置产生的标记形成有效性信号的激光光源的功率。 该信号产生装置包括用于检测来自光学检测器的反射写入脉冲的峰值的模拟峰值检测器，至少一个采样保持电路，用于对反射的写入脉冲进行采样以获得至少一个振幅值;以及处理器， 根据峰值和振幅值产生标记形成有效性信号。

公开(公告)号：US5635878A

公开(公告)日：1997-06-03

申请号：US546406

申请日：1995-10-20

Applicant: Ding-Jen Liu ,  Ying-Tzung Wang

Inventor： Ding-Jen Liu ,  Ying-Tzung Wang

IPC: H03B1/00 ,  H03B1/04 ,  H03B5/24 ,  H03K3/0231 ,  H03L7/099

CPC classification number: H03B5/24 ,  H03K3/0231 ,  H03B2201/02 ,  H03B2202/042

Abstract: A differential-type voltage-controlled oscillator (VCO) with low-frequency stability compensation is disclosed. The differential-type VCO comprises a voltage-to-current converter for converting an input voltage signal into a biasing current signal to control the frequency of the VCO output. The VCO further comprises a number of stages of differential amplifiers connected in cascade. Each of the stages of differential amplifiers includes a pair of differential input PMOS transistors, with each of the PMOS transistors connected to a pair of NMOS load transistors. Each of the pair of NMOS load transistors are connected in parallel. The VCO further comprises a number of stages of bias circuits connected in cascade. Each of the bias circuits is connected to a corresponding stage of the differential amplifiers for receiving the bias current generated by the voltage-to-current converter. Each of the stages of bias circuits comprises a current source for supplying a constant current to maintain the low-frequency voltage-frequency linearity of the output of the VCO, and a biasing PMOS transistor connected in parallel with said current source.

Abstract translation: 公开了一种具有低频稳定性补偿的差分型压控振荡器（VCO）。 差分型VCO包括电压 - 电流转换器，用于将输入电压信号转换成偏置电流信号以控制VCO输出的频率。 VCO还包括级联连接的多级差分放大器。 差分放大器的每个级包括一对差分输入PMOS晶体管，每个PMOS晶体管连接到一对NMOS负载晶体管。 一对NMOS负载晶体管中的每一个并联连接。 VCO还包括级联连接的多级偏置电路。 每个偏置电路连接到差分放大器的相应级，用于接收由电压 - 电流转换器产生的偏置电流。 偏置电路的每个级包括用于提供恒定电流以维持VCO的输出的低频电压 - 频率线性度的电流源和与所述电流源并联连接的偏置PMOS晶体管。