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    Method of manufacturing a MOS integrated circuit having components with different dielectrics
    2.
    发明授权
    Method of manufacturing a MOS integrated circuit having components with different dielectrics 失效
    制造具有不同电介质的元件的MOS集成电路的方法

    公开(公告)号：US6114203A

    公开(公告)日：2000-09-05

    申请号：US644892

    申请日：1996-05-10

    申请人： Gabriella Ghidini ,  Cesare Clementi

    发明人： Gabriella Ghidini ,  Cesare Clementi

    IPC分类号： H01L21/314 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/11526 ,  H01L21/3145 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10844 ,  H01L27/11539

    摘要： The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To improve the quality of the oxide of the cells essentially in terms of resistance to degradation due to the passage of charges through it during the operation of the memory, the method provides for a step for the high-temperature nitriding of the oxide. According to a variant, the nitrided oxide formed on the areas intended for the components of the peripheral circuits is removed and then formed again by a similar thermal oxidation treatment followed by high-temperature nitriding.

    摘要翻译： 所描述的方法提供了在用于存储器单元的硅芯片和存储器的外围电路的其他部件的区域上形成薄热氧化物。 为了提高电池的氧化物的质量，基本上在记忆体的操作期间由于电荷通过它而导致的降解性的降低，该方法提供了氧化物的高温氮化的步骤。 根据一个变型，在用于外围电路的部件的区域上形成的氮化氧化物被除去，然后通过类似的热氧化处理再次形成，然后进行高温氮化。

    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC
    3.
    发明授权
    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC 失效
    用于形成包括非易失性存储器单元和至少两种不同类型的侧晶体管的集成电路以及相应的IC的工艺

    公开(公告)号：US5856221A

    公开(公告)日：1999-01-05

    申请号：US670179

    申请日：1996-06-20

    申请人： Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

    发明人： Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

    IPC分类号： H01L21/8247 ,  H01L27/105

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    摘要： A process or forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor. The process further includes removal of the preceding layer from areas assigned only to the transistors of the second type; deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and formation of a second silicon oxide layer in the areas of both types of peripheral transistors.

    摘要翻译： 一种处理或形成集成电路要求提供至少一个非易失性存储单元矩阵，包括中间电介质层，其包括下部氧化硅层，中间氮化硅层和上部氧化硅层。 该过程要求在至少一个第一和第二晶体管类型的存储器单元外围的区域中同时提供各自具有第一和第二厚度的栅极电介质。 在形成具有栅极氧化层和多晶硅层的电池的浮置栅极以及形成下部氧化硅层和中间氮化硅层之后，根据本发明的方法包括从 基体周边的区域，以及在两种类型的晶体管的区域中在衬底上形成第一氧化硅层。 该方法还包括从仅分配给第二类晶体管的区域中去除前一层; 所述上部氧化硅层在所述第一类型的晶体管的区域中的所述第一氧化硅层和所述第二类型晶体管的区域中的所述衬底之上的所述存储器单元上沉积; 以及在两种类型的外围晶体管的区域中形成第二氧化硅层。

    Nonvolatile floating-gate memory devices, and process of fabrication
    4.
    发明授权
    Nonvolatile floating-gate memory devices, and process of fabrication 失效
    非易失性浮栅存储器件，以及制造工艺

    公开(公告)号：US06448138B1

    公开(公告)日：2002-09-10

    申请号：US09548782

    申请日：2000-04-13

    申请人： Cesare Clementi ,  Gabriella Ghidini ,  Mauro Alessandri

    发明人： Cesare Clementi ,  Gabriella Ghidini ,  Mauro Alessandri

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825

    摘要： A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.

    摘要翻译： 一种制造浮栅存储器件的方法，该方法包括以下步骤：形成包括浮栅区，电介质区和控制栅区的重叠层叠; 以及在所述浮栅区域的侧面上形成氧氮化物的绝缘层，以将所述浮栅区域向外完全密封并改善所述存储器件的保持特性。 在自对准蚀刻层叠层并且注入电池的源极/漏极之后，在浮栅区域的侧面的再氧化期间形成绝缘层。

    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC
    5.
    发明授权
    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC 有权
    用于形成包括非易失性存储单元和侧晶体管和相应IC的集成电路的工艺

    公开(公告)号：US06248630B1

    公开(公告)日：2001-06-19

    申请号：US09300029

    申请日：1999-04-27

    申请人： Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

    发明人： Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

    IPC分类号： H01L218247

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    摘要： A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.

    摘要翻译： 一种用于形成集成电路的工艺包括至少一个非易失性存储单元阵列，其具有至少包含下介电材料层和上氧化硅层的中间介电层。 该集成电路包括至少一个晶体管，同时形成在基体周边的区域中，并且具有第一厚度的栅极电介质。 在形成具有栅极氧化物层和多晶硅层的浮置栅极和形成下部电介质材料层之后，该工艺包括从基体的周边区域去除所述层; 所述上氧化硅层沉积在所述存储器单元上，并在所述外围晶体管的区域中的所述衬底上; 以及至少在周边晶体管的区域中形成第一氧化硅层。 第二晶体管类型可以在连续的步骤中形成具有比所述第一厚度更薄的第二厚度的栅极电介质。

    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC
    7.
    发明授权
    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC 失效
    用于形成包括非易失性存储单元和侧晶体管和相应IC的集成电路的工艺

    公开(公告)号：US6004847A

    公开(公告)日：1999-12-21

    申请号：US667097

    申请日：1996-06-20

    申请人： Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

    发明人： Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

    IPC分类号： H01L21/8247 ,  H01L27/105

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    摘要： A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.

    摘要翻译： 一种用于形成集成电路的工艺包括至少一个非易失性存储单元阵列，其具有至少包含下介电材料层和上氧化硅层的中间介电层。 该集成电路包括至少一个晶体管，同时形成在基体周边的区域中，并且具有第一厚度的栅极电介质。 在形成具有栅极氧化物层和多晶硅层的浮置栅极和形成下部电介质材料层之后，该工艺包括从基体的周边区域去除所述层; 所述上氧化硅层沉积在所述存储单元上，并在所述外围晶体管的区域中的衬底上; 以及至少在周边晶体管的区域中形成第一氧化硅层。 第二晶体管类型可以在连续的步骤中形成具有比所述第一厚度更薄的第二厚度的栅极电介质。