公开(公告)号：US06448138B1

公开(公告)日：2002-09-10

申请号：US09548782

申请日：2000-04-13

申请人： Cesare Clementi ,  Gabriella Ghidini ,  Mauro Alessandri

发明人： Cesare Clementi ,  Gabriella Ghidini ,  Mauro Alessandri

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825

摘要： A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.

摘要翻译： 一种制造浮栅存储器件的方法，该方法包括以下步骤：形成包括浮栅区，电介质区和控制栅区的重叠层叠; 以及在所述浮栅区域的侧面上形成氧氮化物的绝缘层，以将所述浮栅区域向外完全密封并改善所述存储器件的保持特性。 在自对准蚀刻层叠层并且注入电池的源极/漏极之后，在浮栅区域的侧面的再氧化期间形成绝缘层。

公开(公告)号：US5054834A

公开(公告)日：1991-10-08

申请号：US446196

申请日：1989-12-05

申请人： Mauro Alessandri ,  Renzo Carrera ,  Giulio Iannuzzi

发明人： Mauro Alessandri ,  Renzo Carrera ,  Giulio Iannuzzi

IPC分类号： H01L21/687

CPC分类号： H01L21/68707 ,  Y10S294/907

摘要： A gripper for the advantageously robotized handling of one or more silicon wafers (5) comprises a part (2, 102) which allows the gripper (1, 101) to be secured to an operating arm or other handling member (3), the part (2, 102) being rigid with a support structure (4, 104) for the silicon wafers. The structure (4, 104) comprises at least two mutually cooperating opposing jaws (9, 10; 109, 110) mobile relative to each other; the jaws (9, 10; 109, 110) are provided with at least one seat (16, 116) for adapting to the shape of the lateral edge (17) of the wafer (5) supported by the jaws during its handling. Advantageously, on one side (108) of the wafer support structure (104) there are provided at least two members (174) mobile relative to the side (108) and arranged to cooperate with a silicon wafer holder or boat, to enable this latter to be supported and handled.

摘要翻译： 用于有利地自动化处理一个或多个硅晶片（5）的夹持器包括允许夹持器（1,101）固定到操作臂或其他处理构件（3）的部分（2,102），所述部件 （2,102）与用于硅晶片的支撑结构（4,104）是刚性的。 结构（4,104）包括相对于彼此移动的至少两个相互配合的相对的钳口（9,10; 109,110）; 钳口（9,10; 109,110）设置有至少一个座（16,116），用于在其处理期间适应由钳口支撑的晶片（5）的侧边缘（17）的形状。 有利地，在晶片支撑结构（104）的一侧（108）上设置有至少两个可相对于侧面（108）移动的构件（174），并被布置成与硅晶片保持器或舟皿配合，以使后者 得到支持和处理。

公开(公告)号：US06720271B2

公开(公告)日：2004-04-13

申请号：US10189152

申请日：2002-07-02

申请人： Enrico Bellandi ,  Francesco Pipia ,  Mauro Alessandri

发明人： Enrico Bellandi ,  Francesco Pipia ,  Mauro Alessandri

IPC分类号： H01L21302

CPC分类号： H01L21/02071 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/76814

摘要： The present invention relates to a process for removing post-etch residues or polymers from the surface of semiconductor devices which comprises treating the semiconductor device with an aqueous ammonia or ammonium hydroxide solution, optionally containing ozone for a time sufficient to effectively remove said post-etch residues or polymers from the surface of the semiconductor device and rinsing the semiconductor device with ozonized water, i.e. water enriched with ozone, in which water is preferably deionized (ozone-DIW).

摘要翻译： 本发明涉及用于从半导体器件表面去除蚀刻后残留物或聚合物的方法，该方法包括用氨水或氢氧化铵水溶液处理半导体器件，任选地含有臭氧足以有效去除所述后蚀刻 来自半导体器件表面的残留物或聚合物，并用臭氧化水（即，富含臭氧的水）漂洗半导体器件，其中水优选为去离子水（臭氧-DIW）。

公开(公告)号：US20060246665A1

公开(公告)日：2006-11-02

申请号：US11476361

申请日：2006-06-27

申请人： Barbara Crivelli ,  Mauro Alessandri

发明人： Barbara Crivelli ,  Mauro Alessandri

IPC分类号： H01L21/336

CPC分类号： H01L29/511 ,  H01L21/3144 ,  H01L29/40114

摘要： A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

公开(公告)号：US07262098B2

公开(公告)日：2007-08-28

申请号：US10323615

申请日：2002-12-18

申请人： Mauro Alessandri ,  Barbara Crivelli ,  Romina Zonca

发明人： Mauro Alessandri ,  Barbara Crivelli ,  Romina Zonca

IPC分类号： H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A process for manufacturing a non-volatile memory cell having at least one gate region, the process including the steps of depositing a first dielectric layer onto a semiconductor substrate; depositing a first semiconductor layer onto the first dielectric layer to form a floating gate region of the memory cell; and defining the floating gate region of the memory cell in the first semiconductor layer. The process further includes the step of depositing a second dielectric layer onto the first conductive layer, the second dielectric layer having a higher dielectric constant than 10. Also disclosed is a memory cell integrated in a semiconductor substrate and having a gate region that has a dielectric layer formed over a first conductive layer and having a dielectric constant higher than 10.

摘要翻译： 一种用于制造具有至少一个栅极区域的非易失性存储单元的工艺，所述方法包括以下步骤：将第一介电层沉积到半导体衬底上; 在所述第一介电层上沉积第一半导体层以形成所述存储单元的浮动栅区; 以及限定第一半导体层中的存储单元的浮置栅极区。 该方法还包括在第一导电层上沉积第二电介质层的步骤，第二电介质层具有比10更高的介电常数。还公开了集成在半导体衬底中并具有栅极区的存储单元，该栅极区具有电介质 层形成在第一导电层上并具有高于10的介电常数。

公开(公告)号：US07084032B2

公开(公告)日：2006-08-01

申请号：US10356351

申请日：2003-01-30

申请人： Barbara Crivelli ,  Mauro Alessandri

发明人： Barbara Crivelli ,  Mauro Alessandri

IPC分类号： H01L21/336

CPC分类号： H01L29/511 ,  H01L21/28273 ,  H01L21/3144

摘要： A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.