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    SEAL RINGS FOR A WIDE BAND-GAP SEMICONDUCTOR LAYER STACK
    2.
    发明申请
    SEAL RINGS FOR A WIDE BAND-GAP SEMICONDUCTOR LAYER STACK 有权

    公开(公告)号：US20250079345A1

    公开(公告)日：2025-03-06

    申请号：US18242906

    申请日：2023-09-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ian McCallum-Cook ,  Mark Levy ,  Zhong-Xiang He

    IPC: H01L23/58 ,  H01L23/31

    Abstract: Structures including a wide band-gap semiconductor layer stack and methods of forming such structures. The structure comprises a layer stack on a substrate and a first dielectric layer on the layer stack. The layer stack includes semiconductor layers that comprise a wide band-gap semiconductor material. A seal ring includes a trench that penetrates through the first dielectric layer and the layer stack to the substrate, a second dielectric layer that lines the trench, and a conductor layer including first and second portions inside the trench. The trench surrounds portions of the layer stack and the first dielectric layer. The second dielectric layer includes a first portion disposed between the first portion of the conductor layer and the portion of the layer stack, and the second dielectric layer includes a second portion disposed between the second portion of the conductor layer and the portion of the first dielectric layer.

    Single ended sense amplifier with current pulse circuit
    3.
    发明授权
    Single ended sense amplifier with current pulse circuit 有权

    公开(公告)号：US12243614B2

    公开(公告)日：2025-03-04

    申请号：US18046961

    申请日：2022-10-17

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

    TRANSISTOR WITH INTEGRATED TURN-OFF SLEW RATE CONTROL
    4.
    发明申请
    TRANSISTOR WITH INTEGRATED TURN-OFF SLEW RATE CONTROL 有权

    公开(公告)号：US20250070781A1

    公开(公告)日：2025-02-27

    申请号：US18455669

    申请日：2023-08-25

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Santosh Sharma ,  Mei Yu Soh

    IPC: H03K19/003 ,  H03K17/0412

    Abstract: Disclosed circuit structure embodiments include an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistors when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). In some embodiments, the slew rate controller includes: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.

    SEMICONDUCTOR FIN WITH DIVOTS, TRANSISTOR INCLUDING THE SEMICONDUCTOR FIN, MEMORY CELL INCLUDING THE TRANSISTOR, AND ASSOCIATED METHODS
    6.
    发明申请
    SEMICONDUCTOR FIN WITH DIVOTS, TRANSISTOR INCLUDING THE SEMICONDUCTOR FIN, MEMORY CELL INCLUDING THE TRANSISTOR, AND ASSOCIATED METHODS 有权

    公开(公告)号：US20250056783A1

    公开(公告)日：2025-02-13

    申请号：US18448467

    申请日：2023-08-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Meixiong Zhao ,  Hongliang Shen ,  Randy William Mann

    IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

    Abstract: Disclosed semiconductor structures include semiconductor fin(s), each extending from a semiconductor substrate and having opposing sidewalls. Each fin has a lower portion and an upper portion above the lower portion. The lower portion has a base proximal to the semiconductor substrate and divots within the opposing sidewalls at the base. An isolation region is on the semiconductor substrate adjacent to the opposing sidewalls of each fin (e.g., including within the divots). The upper portion of each fin extends above the level of the top surface of the isolation region and can be incorporated into a single-fin or multi-fin fin-type device (e.g., a fin-type field effect transistor (FINFET)). In some embodiments, multiple single-fin and/or multi-fin FINFETs incorporating the upper portions of such fins can be incorporated into a memory cell, such as a static random access memory (SRAM) cell. Also disclosed herein are associated method embodiments.

    Peak voltage detection circuit with reduced charge loss
    8.
    发明授权
    Peak voltage detection circuit with reduced charge loss 有权

    公开(公告)号：US12222376B2

    公开(公告)日：2025-02-11

    申请号：US17815961

    申请日：2022-07-29

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Indranil Som ,  Vaibhav Anantrai Ruparelia ,  Kuppireddy Vasudeva Reddy

    IPC: G01R19/04

    Abstract: Embodiments of the disclosure provide a peak voltage detection circuit with reduced charge loss. A circuit structure of the disclosure includes a peak voltage detector having a first input node coupled to an input line and a second input node coupled to a first electrically actuated switch. The peak voltage detector coupling the first input node and the second input node to an output node, and a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor. The first electrically actuated switch couples the capacitor to the second input node of the peak voltage detector. The input line is coupled to a control node of the first electrically actuated switch and a control node of the second electrically actuated switch.

    Optical receiver photodiode testing using test optical terminal at different location than operational optical terminal
    9.
    发明授权
    Optical receiver photodiode testing using test optical terminal at different location than operational optical terminal 有权

    公开(公告)号：US12222257B2

    公开(公告)日：2025-02-11

    申请号：US17657175

    申请日：2022-03-30

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Hanyi Ding ,  Aidong Yan ,  Rongtao Cao

    IPC: G01M11/00 ,  G02B6/42

    Abstract: A structure for testing a photodiode in a PIC using a grating coupler in optical communication with an optical terminal in a different location of the photodiode from another optical terminal used during operation of the PIC. The photodiode includes an operational optical terminal and a test optical terminal with the test optical terminal in a different location than the operational optical terminal. An optical component is in optical communication with the operational optical terminal of the photodiode and is used during operation of the photodiode and the PIC. A grating coupler is in optical communication with the test optical terminal of the photodiode for testing purposes.

    PHOTONIC COMPONENTS WITH CHAMFERED SIDEWALLS
    10.
    发明申请
    PHOTONIC COMPONENTS WITH CHAMFERED SIDEWALLS 有权

    公开(公告)号：US20250035840A1

    公开(公告)日：2025-01-30

    申请号：US18225709

    申请日：2023-07-25

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Yusheng Bian ,  Kenneth Giewont ,  Takako Hirokawa

    IPC: G02B6/122 ,  G02B6/13

    Abstract: Structures for a photonics chip that include a photonic component and methods of forming such structures. The structure may comprise a photodetector on a substrate and a waveguide core. The photodetector includes a light-absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjoined to the first sidewall at an interior angle. The first sidewall is slanted relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis. The waveguide core includes a tapered section adjacent to the first sidewall and the second sidewall of the light-absorbing layer.

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