公开(公告)号：US09666691B2

公开(公告)日：2017-05-30

申请号：US13608961

申请日：2012-09-10

申请人： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

发明人： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/785

摘要： A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

公开(公告)号：US08835982B2

公开(公告)日：2014-09-16

申请号：US13026519

申请日：2011-02-14

申请人： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin

发明人： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin

IPC分类号： H01L29/72

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66598 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供了在半导体器件中形成改进的轻掺杂源极/漏极特征和源极/漏极特征的处理。 具有改进的轻掺杂源极/漏极特征和源极/漏极特征的半导体器件可以防止或减少缺陷并实现高应变效应。 在至少一个实施例中，轻掺杂源极/漏极特征和源极/漏极特征包括通过外延生长形成的相同的半导体材料。

公开(公告)号：US08765556B2

公开(公告)日：2014-07-01

申请号：US12645834

申请日：2009-12-23

申请人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Chao-Cheng Chen ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung

发明人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Chao-Cheng Chen ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate.

摘要翻译： 本公开提供了一种半导体器件，其包括半导体衬底，设置在衬底的一部分上的栅极结构以及设置在衬底的该部分的任一侧的应变结构，并且由与半导体衬底不同的半导体材料形成。 衬底的部分是具有水平区域的垂直区域和从远离衬底表面的方向从水平区域延伸的垂直区域。

公开(公告)号：US20130068248A1

公开(公告)日：2013-03-21

申请号：US13233568

申请日：2011-09-15

申请人： Ming-Hsi Yeh ,  Kuo-Sheng Chuang ,  Ying-Hsueh Chang Chien ,  Chi-Ming Yang ,  Chin-Hsiang Lin

发明人： Ming-Hsi Yeh ,  Kuo-Sheng Chuang ,  Ying-Hsueh Chang Chien ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC分类号： H01L21/00 ,  C23G1/02 ,  B08B5/02 ,  B08B3/08

CPC分类号： H01L21/02057 ,  H01L21/67051

摘要： The present disclosure provides a method including providing a chamber having a first inlet and a second inlet. A solution of a de-ionized (DI) water and an acid (e.g., a dilute acid) is provided to the chamber via the first inlet. A carrier gas (e.g., N2) is provided to the chamber via the second inlet. The solution and the carrier gas are in the chamber and then from the chamber onto a single semiconductor wafer. In an embodiment, the solution includes a dilute HCl and DI water.

摘要翻译： 本公开提供了一种方法，包括提供具有第一入口和第二入口的室。 通过第一入口向腔室提供去离子（DI）水和酸（例如稀酸）的溶液。 载气（例如，N2）经由第二入口提供给腔室。 溶液和载气在室中，然后从室到单个半导体晶片。 在一个实施方案中，溶液包括稀HCl和去离子水。

公开(公告)号：US08362575B2

公开(公告)日：2013-01-29

申请号：US12831925

申请日：2010-07-07

申请人： Tsz-Mei Kwok ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Hsien-Hsin Lin

发明人： Tsz-Mei Kwok ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Hsien-Hsin Lin

IPC分类号： H01L27/088 ,  H01L21/70 ,  H01L21/02 ,  H01L29/06 ,  H01L29/04 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/7851 ,  H01L21/76 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

公开(公告)号：US20120181625A1

公开(公告)日：2012-07-19

申请号：US13009322

申请日：2011-01-19

申请人： Tsz-Mei KWOK ,  Hsueh-Chang SUNG ,  Kuan-Yu CHEN ,  Hsien-Hsin LIN

发明人： Tsz-Mei KWOK ,  Hsueh-Chang SUNG ,  Kuan-Yu CHEN ,  Hsien-Hsin LIN

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供了用于在半导体器件中形成改进的源极/漏极特征的处理。 具有改善的源极/漏极特征的半导体器件可以防止或减少缺陷并实现由epi层产生的高应变效应。 在一个实施例中，源极/漏极特征包括围绕第一部分的第二部分和在第二部分和半导体衬底之间的第三部分，其中第二部分具有不同于第一和第三部分的组成。

公开(公告)号：US20120132957A1

公开(公告)日：2012-05-31

申请号：US12956090

申请日：2010-11-30

申请人： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/165 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.

摘要翻译： 用于形成高性能应变源极 - 漏极结构的方法包括在衬底上形成栅极结构并且形成靠近栅极结构的凹穴注入区域。 隔板与门结构相邻形成。 干蚀刻形成具有第一轮廓的凹部; 湿蚀刻将凹槽放大到第二轮廓; 并且热蚀刻将凹槽放大到第三轮廓。 然后在具有第三轮廓的凹槽中形成源极 - 漏极结构。

公开(公告)号：US20110210404A1

公开(公告)日：2011-09-01

申请号：US12713573

申请日：2010-02-26

申请人： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

发明人： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/785

摘要： A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

摘要翻译： 一种形成集成电路结构的方法包括在衬底的主表面上提供包括衬底和半导体鳍片的晶片，并且执行沉积步骤以在半导体鳍片的顶表面和侧壁上外延生长外延层，其中 外延层包括半导体材料。 然后执行蚀刻步骤以去除外延层的一部分，其中外延层的剩余部分保留在半导体鳍片的顶表面和侧壁上。

公开(公告)号：US20110108894A1

公开(公告)日：2011-05-12

申请号：US12613714

申请日：2009-11-06

申请人： Hsueh-Chang Sung ,  Hsien-Hsin Lin ,  Kuan-Yu Chen ,  Chien-Chang Su ,  Tsz-Mei Kwok ,  Yi-Fang Pai

发明人： Hsueh-Chang Sung ,  Hsien-Hsin Lin ,  Kuan-Yu Chen ,  Chien-Chang Su ,  Tsz-Mei Kwok ,  Yi-Fang Pai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

摘要： The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.

摘要翻译： 本公开提供了一种制造方法，包括提供半导体衬底; 在基板上形成栅极结构; 执行注入工艺以在所述衬底中形成掺杂区域; 在所述栅极结构的侧壁上形成间隔物; 执行第一蚀刻以在所述衬底中形成凹部，其中所述第一蚀刻去除所述掺杂区域的一部分; 执行第二蚀刻以扩大基板中的凹部，其中第二蚀刻包括蚀刻剂和提高在掺杂区域的剩余部分处的蚀刻速率的催化剂; 并用半导体材料填充凹部。

公开(公告)号：US20110024801A1

公开(公告)日：2011-02-03

申请号：US12795088

申请日：2010-06-07

申请人： Chun-Fai CHENG ,  Hsueh-Chang SUNG ,  Kuan-Yu CHEN ,  Hsien-Hsin LIN ,  Fung Ka HING

发明人： Chun-Fai CHENG ,  Hsueh-Chang SUNG ,  Kuan-Yu CHEN ,  Hsien-Hsin LIN ,  Fung Ka HING

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate.

摘要翻译： 晶体管包括设置在衬底上的栅电极。 至少一个复合应变结构邻近栅电极下方的沟道设置。 所述至少一个复合应变结构包括所述基底内的第一应变区。 第二应变区设置在第一应变区上。 第二应变区域的至少一部分设置在衬底内。