公开(公告)号：US20130001705A1

公开(公告)日：2013-01-03

申请号：US13608961

申请日：2012-09-10

Applicant: Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

Inventor： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

IPC: H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/785

Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Abstract translation: 一种形成集成电路结构的方法包括在衬底的主表面上提供包括衬底和半导体鳍片的晶片，并且执行沉积步骤以在半导体鳍片的顶表面和侧壁上外延生长外延层，其中 外延层包括半导体材料。 然后执行蚀刻步骤以去除外延层的一部分，其中外延层的剩余部分保留在半导体鳍片的顶表面和侧壁上。

公开(公告)号：US20110147846A1

公开(公告)日：2011-06-23

申请号：US12644869

申请日：2009-12-22

Applicant: Chien-Chang Su ,  Hsien-Hsin Lin ,  Tsz-Mei Kwok ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Yi-Fang Pai

Inventor： Chien-Chang Su ,  Hsien-Hsin Lin ,  Tsz-Mei Kwok ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Yi-Fang Pai

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.

Abstract translation: 本公开提供一种制造半导体器件的方法，该半导体器件包括形成多个翅片，翅片通过隔离结构彼此隔离，在每个翅片的一部分上形成栅极结构; 在栅极结构的侧壁上分别形成间隔物，蚀刻每个鳍片的剩余部分，从而形成凹槽，外延生长硅以填充凹槽，包括掺杂选自锗（Ge），铟（In） ，和碳（C），并用n型掺杂剂掺杂硅epi。

公开(公告)号：US20110073952A1

公开(公告)日：2011-03-31

申请号：US12831925

申请日：2010-07-07

Applicant: Tsz-Mei Kwok ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Hsien-Hsin Lin

Inventor： Tsz-Mei Kwok ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Hsien-Hsin Lin

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/76 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

Abstract translation: 集成电路结构包括鳍状物场效应晶体管（FinFET），其包括在绝缘区域上方并邻近绝缘区域的半导体鳍片; 以及绝缘区域上的源极/漏极区域。 源极/漏极区域包括第一和第二半导体区域。 第一半导体区域包括硅和选自锗和碳的元素，其中元素在第一半导体区域中具有第一原子百分比。 第一半导体区域具有上斜面和向下斜面。 第二半导体区域包括硅和元件。 该元素具有比第一原子百分比低的第二原子百分比。 第二半导体区域在上斜面上具有第一部分，并具有第一厚度。 第二半导体区域的第二部分（如果有的话）在下斜面上具有小于第一厚度的第二厚度。

公开(公告)号：US20080246057A1

公开(公告)日：2008-10-09

申请号：US11732889

申请日：2007-04-05

Applicant: Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

Inventor： Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

IPC: H01L29/78

CPC classification number: H01L29/66477 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

Abstract translation: 提供一种复合半导体结构及其形成方法。 复合半导体结构包括第一含硅化合物层，其包含选自基本上由锗和碳组成的组的元素; 所述第一含硅化合物层上的硅层，其中所述硅层包含基本上纯的硅; 以及在所述硅层上包含所述元素的第二含硅化合物层。 第一和第二含硅化合物层具有比硅层低的硅浓度。 复合半导体结构可以形成为金属氧化物半导体（MOS）器件的源极/漏极区域。

公开(公告)号：US08709897B2

公开(公告)日：2014-04-29

申请号：US12956090

申请日：2010-11-30

Applicant: Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

Inventor： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/165 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.

Abstract translation: 用于形成高性能应变源极 - 漏极结构的方法包括在衬底上形成栅极结构并且形成靠近栅极结构的凹穴注入区域。 隔板与门结构相邻形成。 干蚀刻形成具有第一轮廓的凹部; 湿蚀刻将凹槽放大到第二轮廓; 并且热蚀刻将凹槽放大到第三轮廓。 然后在具有第三轮廓的凹槽中形成源极 - 漏极结构。

公开(公告)号：US08558289B2

公开(公告)日：2013-10-15

申请号：US12795088

申请日：2010-06-07

Applicant: Chun-Fai Cheng ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Fung Ka Hing

Inventor： Chun-Fai Cheng ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Fung Ka Hing

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate.

Abstract translation: 晶体管包括设置在衬底上的栅电极。 至少一个复合应变结构邻近栅电极下方的沟道设置。 所述至少一个复合应变结构包括所述基底内的第一应变区。 第二应变区设置在第一应变区上。 第二应变区域的至少一部分设置在衬底内。

公开(公告)号：US08487354B2

公开(公告)日：2013-07-16

申请号：US12545705

申请日：2009-08-21

Applicant: Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Chun-Feng Nieh ,  Hsueh-Chang Sung ,  Chien-Chang Su ,  Tsz-Mei Kwok

Inventor： Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Chun-Feng Nieh ,  Hsueh-Chang Sung ,  Chien-Chang Su ,  Tsz-Mei Kwok

IPC: H01L29/76

CPC classification number: H01L29/66477 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.

Abstract translation: 本公开提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底上形成栅极结构，在衬底上形成材料层和栅极结构，将Ge，C，P，F或B注入 所述材料层，去除所述栅极结构的任一侧上覆盖所述衬底的所述材料层的部分，在所述栅极结构的任一侧上在所述衬底中形成凹陷，以及通过开晶过程在所述凹部中沉积半导体材料。

公开(公告)号：US08404538B2

公开(公告)日：2013-03-26

申请号：US12572743

申请日：2009-10-02

Applicant: Kao-Ting Lai ,  Da-Wen Lin ,  Hsien-Hsin Lin ,  Yuan-Ching Peng ,  Chi-Hsi Wu

Inventor： Kao-Ting Lai ,  Da-Wen Lin ,  Hsien-Hsin Lin ,  Yuan-Ching Peng ,  Chi-Hsi Wu

IPC: H01L21/8238

CPC classification number: H01L21/3247 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

Abstract translation: 一种方法包括提供包括衬底材料的衬底，在衬底上方的栅极电介质膜和与栅极电介质膜相邻的第一间隔物。 间隔物具有与基底的表面接触的第一部分和与栅极电介质膜的一侧接触的第二部分。 在与衬垫相邻的衬底的区域中形成凹部。 凹部由基底材料的第一侧壁限定。 第一侧壁的至少一部分位于间隔件的至少一部分的下面。 衬垫材料位于衬垫的第一部分下面被回流，使得限定凹陷的衬底材料的第一侧壁的顶部基本上与栅极电介质膜和间隔物之间​​的边界对齐。 凹陷部分填充有压力源材料。

公开(公告)号：US20130023094A1

公开(公告)日：2013-01-24

申请号：US13189108

申请日：2011-07-22

Applicant: Ming-Hsi YEH ,  Hsien-Hsin LIN ,  Ying-Hsueh CHANG CHIEN ,  Yi-Fang PAI ,  Chi-Ming YANG ,  Chin-Hsiang LIN

Inventor： Ming-Hsi YEH ,  Hsien-Hsin LIN ,  Ying-Hsueh CHANG CHIEN ,  Yi-Fang PAI ,  Chi-Ming YANG ,  Chin-Hsiang LIN

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  Y10S438/976

Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.

Abstract translation: 公开了一种用于制造集成器件的方法。 当形成与由保护层未覆盖的另一个栅极结构相邻的外延（epi）特征时，在栅极结构上形成保护层。 此后，在形成外延（epi）特征之后，去除保护层。 所公开的方法提供了用于去除保护层而没有实质缺陷的改进方法。 在一个实施方案中，改进的形成方法通过在氧化物基材料上提供保护剂，然后使用包含氢氟酸的化学品除去保护层来实现。

公开(公告)号：US08344447B2

公开(公告)日：2013-01-01

申请号：US11732889

申请日：2007-04-05

Applicant: Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

Inventor： Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

IPC: H01L29/94

CPC classification number: H01L29/66477 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

Abstract translation: 提供一种复合半导体结构及其形成方法。 复合半导体结构包括第一含硅化合物层，其包含选自基本上由锗和碳组成的组的元素; 所述第一含硅化合物层上的硅层，其中所述硅层包含基本上纯的硅; 以及在所述硅层上包含所述元素的第二含硅化合物层。 第一和第二含硅化合物层具有比硅层低的硅浓度。 复合半导体结构可以形成为金属氧化物半导体（MOS）器件的源极/漏极区域。