公开(公告)号：US08680841B2

公开(公告)日：2014-03-25

申请号：US12983090

申请日：2010-12-31

Applicant: Jeong Hun Lee ,  Yong Mi Kim ,  Jeong Tae Hwang

Inventor： Jeong Hun Lee ,  Yong Mi Kim ,  Jeong Tae Hwang

IPC: G05F1/607 ,  G05F1/614

CPC classification number: G11C5/147 ,  G11C29/021

Abstract: A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.

Abstract translation: 一种半导体装置，包括：被配置为生成多个不同的比较电压的比较电压生成单元，被配置为从外部系统接收生成代码的基准电压生成单元，根据生成代码选择所述多个不同的比较电压中的一个 并产生参考电压，参考电压确定单元被配置为从外部系统接收生成代码和预期参考电压，检查预期参考电压的电平是否在目标范围内，并将检查结果输出到 外部系统。

公开(公告)号：US08659962B2

公开(公告)日：2014-02-25

申请号：US13404446

申请日：2012-02-24

Applicant: Jeong-Hun Lee

Inventor： Jeong-Hun Lee

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C8/00

CPC classification number: G11C29/021 ,  G11C11/40 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/40 ,  G11C29/48

Abstract: A semiconductor device includes a data storage unit configured to receive input data, outputs the input data with a difference in voltage level between logic levels, and output comparison data whose logic level is distinguished from the input data; a test operation unit configured to determine a logic level of test data periodically in response to a data reference voltage whose voltage level is determined in response to a level test code during a test operation period defined by a test entry command and a test exit command, and generate a test result signal by comparing a logic level of the comparison data with the logic level of the test data; and a test operation sensing signal generation unit configured to generate a test operation sensing signal that is activated in response to the test entry command and inactivated in response to the test result signal.

Abstract translation: 半导体器件包括：数据存储单元，被配置为接收输入数据，输出具有逻辑电平之间的电压电平差的输入数据，以及逻辑电平与输入数据区分的输出比较数据; 测试操作单元，被配置为响应于在由测试输入命令和测试退出命令所定义的测试操作期间响应于电平测试代码确定其电压电平的数据参考电压周期性地确定测试数据的逻辑电平， 并通过将比较数据的逻辑电平与测试数据的逻辑电平进行比较来产生测试结果信号; 以及测试操作感测信号生成单元，被配置为生成响应于测试输入命令被激活并且响应于测试结果信号而被去激活的测试操作感测信号。

公开(公告)号：US08589988B2

公开(公告)日：2013-11-19

申请号：US12947448

申请日：2010-11-16

Applicant: Jeong-hun Lee

Inventor： Jeong-hun Lee

IPC: H04N7/18

CPC classification number: H04N21/2143 ,  G06F3/1423 ,  G09G5/003 ,  G09G2320/08 ,  G09G2330/02 ,  G09G2370/04 ,  H04N21/2383 ,  H04N21/4333 ,  H04N21/4382

Abstract: A method for converting a sink device and an apparatus for providing a content using the same are provided. The method for converting the sink device includes receiving a sink device conversion command from a first sink device, transmitting the content to a second sink device if a conversion approval of the sink device is received from the second sink device, and transmitting a control authority related to a content provision from the first sink device to the second sink device.

Abstract translation: 提供了一种用于转换宿设备的方法和用于提供使用其的设备的设备。 用于转换宿设备的方法包括从第一宿设备接收宿设备转换命令，如果从第二宿设备接收到宿设备的转换许可，则将内容传送到第二宿设备，并且发送控制权限相关 涉及从第一宿设备到第二宿设备的内容提供。

公开(公告)号：US08386858B2

公开(公告)日：2013-02-26

申请号：US12616529

申请日：2009-11-11

Applicant: Jeong-Hun Lee ,  Jeong-Tae Hwang

Inventor： Jeong-Hun Lee ,  Jeong-Tae Hwang

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/46

Abstract: A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.

Abstract translation: 半导体存储器件能够在其各种操作模式下执行测试操作。 特别地，半导体存储器件可以进入其他模式的测试模式以及全部银行预充电模式。 半导体存储器件包括：测试模式控制块，被配置为在激活模式下产生预定间隔使能的测试信号;以及模式寄存器组控制模块，被配置为使得模式寄存器设置信号能够在预定间隔内进行测试操作 响应测试信号。

公开(公告)号：US20130001948A1

公开(公告)日：2013-01-03

申请号：US13468218

申请日：2012-05-10

Applicant: Chan-Sun LIM ,  Myeong-Hyo KIM ,  Jong-Sub SHIN ,  Young-Chang SHON ,  Jeong-Hun LEE

Inventor： Chan-Sun LIM ,  Myeong-Hyo KIM ,  Jong-Sub SHIN ,  Young-Chang SHON ,  Jeong-Hun LEE

IPC: H02K7/18 ,  F02C6/02 ,  F02C6/16 ,  F15B1/033 ,  F02C1/04

CPC classification number: F02C7/08 ,  F02C6/16 ,  Y02E60/15

Abstract: A power generation system includes a compression unit which compresses a gas, a storage which stores the compressed gas output from the compression unit, a first expansion unit which generates first power and outputs a first exhaust gas, a heating unit which heats at least the stored gas output from the storage, a second expansion unit which generates second power and outputs a second exhaust gas, a first regenerator which performs a first heat exchange between the second exhaust gas and the stored gas output from the storage, to generate a first heat exchange gas used to generate the first power and a first regenerator gas, and a second regenerator which performs a second heat exchange between the first exhaust gas and the first regenerator gas to generate a second heat exchange gas used to generate the second power after heated at the heating unit.

Abstract translation: 发电系统包括压缩气体的压缩单元，存储从压缩单元输出的压缩气体的存储器，产生第一功率并输出第一排气的第一膨胀单元，至少加热存储的加热单元 从存储器输出的气体，产生第二功率并输出第二废气的第二膨胀单元，在第二排气和从储存器输出的储存气体之间进行第一热交换的第一再生器，以产生第一热交换 用于产生第一功率的气体和第一再生器气体;以及第二再生器，其在第一废气和第一再生器气体之间进行第二热交换，以产生用于在第一再生器加热后产生第二功率的第二热交换气体 加热单元

公开(公告)号：US20120155203A1

公开(公告)日：2012-06-21

申请号：US13104262

申请日：2011-05-10

Applicant: Jeong-Tae Hwang ,  Jeong-Hun Lee

Inventor： Jeong-Tae Hwang ,  Jeong-Hun Lee

IPC: G11C29/18

CPC classification number: G11C29/28

Abstract: A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.

Abstract translation: 一种测试半导体存储器件的方法包括通过通道从测试设备接收时钟，地址，命令和数据，响应于地址和命令产生内部存储体地址，对每一个执行多位并行测试 基于地址，命令，数据和内部存储体地址的多个存储体，以及向测试装置提供测试结果信号。

公开(公告)号：US20120044780A1

公开(公告)日：2012-02-23

申请号：US12983185

申请日：2010-12-31

Applicant: Yong Mi KIM ,  Jeong Hun LEE

Inventor： Yong Mi KIM ,  Jeong Hun LEE

IPC: G11C8/18

CPC classification number: G11C7/1057 ,  G11C7/1066 ,  G11C8/18

Abstract: A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data.

Abstract translation: 半导体存储装置的数据输出电路包括：数据控制驱动器，被配置为驱动上升数据和下降数据以输出控制上升数据并控制下降数据或驱动电平数据以输出控制上升数据和控制下降数据 到输出电平测试信号; DLL时钟控制单元，被配置为响应于使能信号和输出电平测试信号驱动上升时钟和下降时钟以输出控制上升时钟和控制下降时钟; 以及时钟同步单元，被配置为使控制上升数据和控制下降数据与控制上升时钟和控制下降时钟同步，以输出串行上升数据和串行下降数据。

公开(公告)号：US07983106B2

公开(公告)日：2011-07-19

申请号：US12494815

申请日：2009-06-30

Applicant: Yong-Mi Kim ,  Jeong-Tea Hwang ,  Jeong-Hun Lee

Inventor： Yong-Mi Kim ,  Jeong-Tea Hwang ,  Jeong-Hun Lee

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/02 ,  G11C7/22 ,  G11C7/222

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract translation: 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。

公开(公告)号：US09053772B2

公开(公告)日：2015-06-09

申请号：US13315483

申请日：2011-12-09

Applicant: Jeong Hun Lee

Inventor： Jeong Hun Lee

IPC: G11C5/14 ,  G11C7/10

CPC classification number: G11C5/147 ,  G11C7/1084 ,  G11C7/1087

Abstract: A method for conducting reference voltage training includes setting levels of a reference voltage in response to code signals and receiving and storing data for the respective levels of the reference voltage, and simultaneously outputting the stored data.

Abstract translation: 用于进行参考电压训练的方法包括响应于代码信号设置参考电压的电平，并且接收和存储参考电压的各个电平的数据，并同时输出所存储的数据。

公开(公告)号：US08503260B2

公开(公告)日：2013-08-06

申请号：US13104262

申请日：2011-05-10

Applicant: Jeong-Tae Hwang ,  Jeong-Hun Lee

Inventor： Jeong-Tae Hwang ,  Jeong-Hun Lee

IPC: G11C29/00 ,  G11C8/00

CPC classification number: G11C29/28

Abstract: A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.

Abstract translation: 一种测试半导体存储器件的方法包括通过通道从测试设备接收时钟，地址，命令和数据，响应于地址和命令产生内部存储体地址，对每一个执行多位并行测试 基于地址，命令，数据和内部存储体地址的多个存储体，以及向测试装置提供测试结果信号。