公开(公告)号：US20100117120A1

公开(公告)日：2010-05-13

申请号：US12689723

申请日：2010-01-19

申请人： Kyouji YAMASHITA

发明人： Kyouji YAMASHITA

IPC分类号： H01L27/092

CPC分类号： H01L21/823878 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

摘要： A semiconductor device includes a first well region 3a; a second well region 3b; a first active region 21a surrounded by an isolation region 2; a second active region 21b surrounded by the isolation regions 2 and 2B; a first MIS transistor MP2 of a second conductivity type formed on the first active region 21a; and including a source/drain region formed of a Si mixed crystal layer buried in a recess; a second MIS transistor MN2 of a first conductivity type formed on the second active region 21b; and an isolation MIS transistor DP2 of the second conductivity type formed on the first active region 21a. The source/drain region of the first MIS transistor is not in contact with the isolation region 2 located at an end of the first active region 21a in a gate length direction.

摘要翻译： 半导体器件包括第一阱区域3a; 第二井区域3b; 由隔离区域2包围的第一有源区域21a; 由隔离区域2和2B包围的第二活性区域21b; 形成在第一有源区域21a上的第二导电类型的第一MIS晶体管MP2; 并且包括由埋在凹部中的Si混合晶体层形成的源极/漏极区域; 形成在第二有源区域21b上的第一导电类型的第二MIS晶体管MN2; 以及形成在第一有源区域21a上的第二导电类型的隔离MIS晶体管DP2。 第一MIS晶体管的源极/漏极区域不与栅极长度方向上位于第一有源区域21a的端部处的隔离区域2接触。

公开(公告)号：US20130334608A1

公开(公告)日：2013-12-19

申请号：US13942546

申请日：2013-07-15

申请人： Daisaku IKOMA ,  Yoshinao HARADA ,  Kyouji YAMASHITA ,  Katsuhiro OOTANI

发明人： Daisaku IKOMA ,  Yoshinao HARADA ,  Kyouji YAMASHITA ,  Katsuhiro OOTANI

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/28088 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/7833

摘要： A semiconductor device includes a first transistor formed on a semiconductor substrate, and including a first channel region, and a first gate electrode formed on the first channel region, and a second transistor formed on the semiconductor substrate, and including a second channel region having a conductivity type identical to a conductivity type of the first channel region, and a second gate electrode formed on the second channel region and having a potential identical to a potential of the first gate electrode. A drain of the first transistor is electrically connected to a source of the second transistor. An absolute value of a threshold voltage of the first transistor is greater than an absolute value of a threshold voltage of the second transistor.

摘要翻译： 半导体器件包括形成在半导体衬底上并包括第一沟道区的第一晶体管和形成在第一沟道区上的第一栅极，以及形成在半导体衬底上的第二晶体管，并且包括第二沟道区， 导电类型与第一沟道区的导电类型相同，第二栅电极形成在第二沟道区上并具有与第一栅电极的电位相同的电位。 第一晶体管的漏极电连接到第二晶体管的源极。 第一晶体管的阈值电压的绝对值大于第二晶体管的阈值电压的绝对值。

公开(公告)号：US20100059801A1

公开(公告)日：2010-03-11

申请号：US12538534

申请日：2009-08-10

申请人： Masayuki Kamei ,  Kyouji Yamashita ,  Daisaku Ikoma

发明人： Masayuki Kamei ,  Kyouji Yamashita ,  Daisaku Ikoma

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  Y10S257/90

摘要： A semiconductor device includes a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; an offset spacer formed on a side surface of the gate electrode; an inner sidewall formed on the side surface of the gate electrode with the offset spacer interposed therebetween, and having an L-shaped cross section; and an insulating film formed to cover the gate electrode, the offset spacer, the inner sidewall, and a part of the semiconductor region located laterally outward from the inner sidewall. The offset spacer includes an inner offset spacer formed on the side surface of the gate electrode and an outer offset spacer formed to cover the side surface of the gate electrode and the inner offset spacer. The outer offset spacer is in contact with a top end and outer side surface of the inner offset spacer.

摘要翻译： 半导体器件包括形成在第一导电类型的半导体区域上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 形成在所述栅电极的侧面上的偏移间隔物; 在所述栅电极的侧面上形成有所述偏移间隔物的内侧壁，并具有L形截面; 以及绝缘膜，形成为覆盖从内侧壁侧向外侧的栅电极，偏移间隔件，内侧壁和半导体区域的一部分。 偏移间隔件包括形成在栅电极的侧表面上的内偏移间隔件和形成为覆盖栅电极的侧表面和内偏移间隔件的外偏移间​​隔件。 外部偏移间隔件与内部偏移间隔件的顶端和外侧表面接触。

公开(公告)号：US08555224B2

公开(公告)日：2013-10-08

申请号：US13471061

申请日：2012-05-14

申请人： Tomoyuki Ishizu ,  Kyouji Yamashita ,  Gaku Suzuki

发明人： Tomoyuki Ishizu ,  Kyouji Yamashita ,  Gaku Suzuki

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5036

摘要： The present disclosure provides a method of performing circuit simulation of electrical characteristics of a transistor formed on a semiconductor substrate using calculators, each of which includes a memory. A first calculator receives mask layout data and distance-dependent data indicating a distance from the target transistor. Then, a second calculator calculates an area ratio of a layout pattern of a predetermined mask from the received mask layout data, and calculates a parameter α based on the area ratio and the distance-dependent data. Then, the second calculator B calculates a change ΔP in the electrical characteristics of the transistor based on the parameter α. This configuration provides highly accurate circuit simulation of the electrical characteristics of the transistor, which depend on variations in temperature distribution of the semiconductor substrate during heat treatment due to the mask layout pattern around the transistor.

摘要翻译： 本公开提供了一种使用计算器来执行形成在半导体衬底上的晶体管的电特性的电路仿真的方法，每个都包括存储器。 第一计算器接收掩模布局数据和指示距离目标晶体管的距离的距离相关数据。 然后，第二计算器从接收到的掩模布局数据计算预定掩模的布局图案的面积比，并且基于面积比和距离相关数据计算参数α。 然后，第二计算器B基于参数α计算晶体管的电特性中的变化ΔP。 该配置提供了晶体管的电特性的高度精确的电路仿真，其取决于由于晶体管周围的掩模布局图案而在热处理期间半导体衬底的温度分布的变化。

公开(公告)号：US20120227016A1

公开(公告)日：2012-09-06

申请号：US13471061

申请日：2012-05-14

申请人： Tomoyuki ISHIZU ,  Kyouji YAMASHITA ,  Gaku SUZUKI

发明人： Tomoyuki ISHIZU ,  Kyouji YAMASHITA ,  Gaku SUZUKI

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5036

摘要： The present disclosure provides a method of performing circuit simulation of electrical characteristics of a transistor formed on a semiconductor substrate using calculators, each of which includes a memory. A first calculator receives mask layout data and distance-dependent data indicating a distance from the target transistor. Then, a second calculator calculates an area ratio of a layout pattern of a predetermined mask from the received mask layout data, and calculates a parameter α based on the area ratio and the distance-dependent data. Then, the second calculator B calculates a change ΔP in the electrical characteristics of the transistor based on the parameter α. This configuration provides highly accurate circuit simulation of the electrical characteristics of the transistor, which depend on variations in temperature distribution of the semiconductor substrate during heat treatment due to the mask layout pattern around the transistor.

摘要翻译： 本公开提供了一种使用计算器来执行形成在半导体衬底上的晶体管的电特性的电路仿真的方法，每个都包括存储器。 第一计算器接收掩模布局数据和指示距离目标晶体管的距离的距离相关数据。 然后，第二计算器从接收到的掩模布局数据计算预定掩模的布局图案的面积比，并且基于面积比和距离相关数据来计算参数α。 然后，第二计算器B基于参数α计算晶体管的电特性中的变化＆Dgr; P。 该配置提供了晶体管的电特性的高度精确的电路仿真，其取决于由于晶体管周围的掩模布局图案而在热处理期间半导体衬底的温度分布的变化。

公开(公告)号：US08237205B2

公开(公告)日：2012-08-07

申请号：US12538534

申请日：2009-08-10

申请人： Masayuki Kamei ,  Kyouji Yamashita ,  Daisaku Ikoma

发明人： Masayuki Kamei ,  Kyouji Yamashita ,  Daisaku Ikoma

IPC分类号： H01L29/76

CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  Y10S257/90

摘要： A semiconductor device includes a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; an offset spacer formed on a side surface of the gate electrode; an inner sidewall formed on the side surface of the gate electrode with the offset spacer interposed therebetween, and having an L-shaped cross section; and an insulating film formed to cover the gate electrode, the offset spacer, the inner sidewall, and a part of the semiconductor region located laterally outward from the inner sidewall. The offset spacer includes an inner offset spacer formed on the side surface of the gate electrode and an outer offset spacer formed to cover the side surface of the gate electrode and the inner offset spacer. The outer offset spacer is in contact with a top end and outer side surface of the inner offset spacer.

摘要翻译： 半导体器件包括形成在第一导电类型的半导体区域上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 形成在所述栅电极的侧面上的偏移间隔物; 在所述栅电极的侧面上形成有所述偏移间隔物的内侧壁，并具有L形截面; 以及绝缘膜，形成为覆盖从内侧壁侧向外侧的栅电极，偏移间隔件，内侧壁和半导体区域的一部分。 偏移间隔件包括形成在栅电极的侧表面上的内偏移间隔件和形成为覆盖栅电极的侧表面和内偏移间隔件的外偏移间​​隔件。 外部偏移间隔件与内部偏移间隔件的顶端和外侧表面接触。

公开(公告)号：US08217429B2

公开(公告)日：2012-07-10

申请号：US12689723

申请日：2010-01-19

申请人： Kyouji Yamashita

发明人： Kyouji Yamashita

IPC分类号： H01L27/092

CPC分类号： H01L21/823878 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

摘要： A semiconductor device includes a first well region 3a; a second well region 3b; a first active region 21a surrounded by an isolation region 2; a second active region 21b surrounded by the isolation regions 2 and 2B; a first MIS transistor MP2 of a second conductivity type formed on the first active region 21a; and including a source/drain region formed of a Si mixed crystal layer buried in a recess; a second MIS transistor MN2 of a first conductivity type formed on the second active region 21b; and an isolation MIS transistor DP2 of the second conductivity type formed on the first active region 21a. The source/drain region of the first MIS transistor is not in contact with the isolation region 2 located at an end of the first active region 21a in a gate length direction.

摘要翻译： 半导体器件包括第一阱区域3a; 第二井区域3b; 由隔离区域2包围的第一有源区域21a; 由隔离区域2和2B包围的第二活性区域21b; 形成在第一有源区域21a上的第二导电类型的第一MIS晶体管MP2; 并且包括由埋在凹部中的Si混合晶体层形成的源极/漏极区域; 形成在第二有源区域21b上的第一导电类型的第二MIS晶体管MN2; 以及形成在第一有源区域21a上的第二导电类型的隔离MIS晶体管DP2。 第一MIS晶体管的源极/漏极区域不与栅极长度方向上位于第一有源区域21a的端部处的隔离区域2接触。