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公开(公告)号：US07869542B2
公开(公告)日：2011-01-11
申请号：US11671423
申请日：2007-02-05
Applicant: Serge F. Drogi , Vikas Vinayak , Mark R. Gehring , Martin A. Tomasz
Inventor： Serge F. Drogi , Vikas Vinayak , Mark R. Gehring , Martin A. Tomasz
IPC: H04L25/00
CPC classification number: H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042
Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.
Abstract translation: 一种系统，包括相位比较器，用于比较第一信号和第二信号以产生相位误差信号;以及控制器，响应于所述第一信号中的至少一个的振幅，从所述相位误差信号产生经调整的相位误差信号 和第二个信号。
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公开(公告)号：US20100201402A1
公开(公告)日：2010-08-12
申请号：US12761258
申请日：2010-04-15
Applicant: Serge F. Drogi , Vikas Vinayak , Mark R. Gehring , Martin A. Tomasz
Inventor： Serge F. Drogi , Vikas Vinayak , Mark R. Gehring , Martin A. Tomasz
IPC: G01R25/00
CPC classification number: H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042
Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.
Abstract translation: 一种系统，包括相位比较器，用于比较第一信号和第二信号以产生相位误差信号;以及控制器，响应于所述第一信号中的至少一个的振幅，从所述相位误差信号产生经调整的相位误差信号 和第二个信号。
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公开(公告)号：US07642845B2
公开(公告)日：2010-01-05
申请号：US11467067
申请日：2006-08-24
Applicant: Mark R. Gehring , Joseph Stenger
Inventor： Mark R. Gehring , Joseph Stenger
IPC: G01R19/00
CPC classification number: H03F3/191 , H03F3/45475 , H03F2200/453 , H03F2203/45288
Abstract: Systems and method for tracking different types of transconductance cells is shown and described. In these multi-cell systems, the addition of one or more tracking control modules allows circuit designers to advantageously incorporate multiple transconductor topologies and their uniquely beneficial characteristics into their designs, without eradicating its centralized multi-cell tuning functionality.
Abstract translation: 示出并描述了用于跟踪不同类型的跨导单元的系统和方法。 在这些多单元系统中，添加一个或多个跟踪控制模块允许电路设计者有利地将多个跨导体拓扑及其独特的有益特征结合到其设计中，而无需消除其集中的多单元调谐功能。
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公开(公告)号：US07564923B2
公开(公告)日：2009-07-21
申请号：US11261166
申请日：2005-10-27
Applicant: Mark R. Gehring , Russell R. Moen , Brent R. Jensen
Inventor： Mark R. Gehring , Russell R. Moen , Brent R. Jensen
CPC classification number: H04L27/2092
Abstract: A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include as part of a transmitter circuit, a transmit DSP circuit that has the LUT, accumulator and device providing an n-bit signed constant to the accumulator to offset a transmit frequency in order to allow a receiver circuit on the transceiver to communicate directly with the transmitter circuit, and thus allowing testing of the transceiver.
Abstract translation: 发射机数字信号处理器（DSP）电路具有由查找表（LUT）输出的n位数据表示的发射频率。 n比特数据被输出到构成为以基于输出n比特数据的速率溢出的n比特累加器，以输出相位。 电路还具有被构造为向累加器添加n位有符号常数以便偏移由LUT输出的n位数据表示的频率的器件。 半导体芯片上的收发器可以包括作为发射机电路的一部分的发射DSP电路，其具有LUT，累加器和设备向累加器提供n位有符号常数以偏移发射频率，以允许接收机电路 收发器与发射机电路直接通信，从而允许对收发器进行测试。
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公开(公告)号：US07107036B1
公开(公告)日：2006-09-12
申请号：US10295662
申请日：2002-11-15
Applicant: Mark R. Gehring
Inventor： Mark R. Gehring
IPC: H04B1/16
Abstract: Embodiments of a frequency modulated (FM) demodulator and associated methods are generally described. According to but one example embodiment, an apparatus is disclosed comprising a receiver front-end, to receive a signal from one or more antenna(e) and generate quadrature components of the received signal, and a frequency-shifted, cross-multiplied differentiator demodulator, coupled with the receiver front-end, to generate a demodulated representation of the received signal centered at a select intermediate frequency.
Abstract translation: 通常描述调频（FM）解调器和相关方法的实施例。 根据但是一个示例性实施例，公开了一种包括接收机前端的装置，用于从一个或多个天线（e）接收信号并产生接收信号的正交分量，以及频移的十字乘法微分解调器 与接收器前端耦合以产生以选择中频为中心的接收信号的解调表示。
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Patent Agency Ranking
公开(公告)号：US5134724A
公开(公告)日：1992-07-28
申请号：US520650
申请日：1990-05-08
Applicant: Mark R. Gehring , Richard R. Suter , Lawrence H. Ragan
Inventor： Mark R. Gehring , Richard R. Suter , Lawrence H. Ragan
Abstract: A wrist band for a wrist-mounted radio system is provided wherein a metallic wrist-band buckle need not be insulated. The system includes a radio receiver which includes a differential input in a wrist-band antenna with a "null point" at the location of the buckle. The wrist-band antenna is insulated from the wearer's body at all points except at the buckle.
Abstract translation: 提供了一种用于腕上无线电系统的腕带，其中金属腕带带扣不需要绝缘。 该系统包括无线电接收机，该无线电接收机包括带扣天线的差分输入，在带扣位置具有“零点”。 手腕带天线除扣带外的所有点与佩戴者的身体绝缘。
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公开(公告)号：US07660563B2
公开(公告)日：2010-02-09
申请号：US11532592
申请日：2006-09-18
Applicant: Mark R. Gehring , Brent R. Jensen
Inventor： Mark R. Gehring , Brent R. Jensen
CPC classification number: H03D7/1425 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0047
Abstract: A circuit including a subcircuit having differential signals, and a feedback circuit coupled to the subcircuit. The feedback circuit is configured to measure an offset between the differential signals, to generate a calibration signal in response to the measurement, and to reduce the offset in response to the calibration signal.
Abstract translation: 包括具有差分信号的分支电路的电路和耦合到子电路的反馈电路。 反馈电路被配置为测量差分信号之间的偏移，以响应于测量而产生校准信号，并且响应于校准信号而减小偏移。
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公开(公告)号：US06903613B1
公开(公告)日：2005-06-07
申请号：US10327354
申请日：2002-12-20
Applicant: Eric P. Mitchell , Mark R. Gehring
Inventor： Eric P. Mitchell , Mark R. Gehring
Abstract: Embodiments of the present invention provide a method of centering an operating band of a voltage controlled oscillator around a desired operating frequency. In one embodiment, an adjustable feedback divider provides for driving an output signal to the top and bottom of the operating band. An adjustable period divider and counter provide a plurality of count values for use in determining a mid-point of the operating band. A capacitance bank provides for selectively adjusting a capacitance of the voltage controlled oscillator, thereby adjusting the operating band.
Abstract translation: 本发明的实施例提供一种围绕期望的工作频率使压控振荡器的工作频带居中的方法。 在一个实施例中，可调节反馈分频器用于将输出信号驱动到操作频带的顶部和底部。 可调周期分频器和计数器提供用于确定工作频带中点的多个计数值。 电容组提供选择性地调节压控振荡器的电容，从而调整工作频带。
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公开(公告)号：US06744323B1
公开(公告)日：2004-06-01
申请号：US09943149
申请日：2001-08-30
Applicant: Nathan Y. Moyal , Mark R. Gehring , Russell Moen , Lawrence Ragan
Inventor： Nathan Y. Moyal , Mark R. Gehring , Russell Moen , Lawrence Ragan
IPC: H03L700
CPC classification number: H03L7/10 , H03L7/095 , H03L7/18 , Y10S331/02
Abstract: An apparatus comprising a phase lock loop (PLL) and a lock circuit. The PLL may be configured to multiply an input frequency in response to a lock signal. The lock circuit may be configured to generate the lock signal. The PLL may also be configured to select a reference frequency as (i) the input frequency when in a first mode and (ii) a divided frequency of the input frequency when in a second mode.
Abstract translation: 一种包括锁相环（PLL）和锁电路的装置。 PLL可以被配置为响应于锁定信号来乘以输入频率。 锁定电路可以被配置为产生锁定信号。 PLL还可以被配置为在第一模式中选择参考频率为（i）输入频率，以及（ii）当处于第二模式时输入频率的分频。
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公开(公告)号：US5404322A
公开(公告)日：1995-04-04
申请号：US863313
申请日：1992-03-27
Applicant: Mark R. Gehring
Inventor： Mark R. Gehring
CPC classification number: H03H17/06
Abstract: A digital filter is designed by characterizing a desired filter passband in the frequency domain, transforming this representation into the time domain, selecting weighting coefficients at periodically spaced intervals from this transformed function, and weighting the coefficients with a Gaussian windowing function. This function may take the form:.sub.e -.vertline.( 2 n-N)/A.vertline..sup.Pwhere:A=N(-ln.epsilon.).sup.-1/P; .epsilon.
Abstract translation: 通过在频域中表征期望的滤波器通带来设计数字滤波器，将该表示变换为时域，从该变换函数中选择以周期性间隔的间隔的加权系数，并用高斯窗口函数对系数进行加权。 该函数可以采用以下形式：e- |（2 n-N）/ A | P其中：A = N（-lnε）-1 / P; epsilon <1 epsilon = n = 0和n = N（缩小比）所需的窗口值; N =（F.I.R.抽头数）-1; 而P =任意幂。
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