公开(公告)号：US07774580B2

公开(公告)日：2010-08-10

申请号：US11077561

申请日：2005-03-11

Applicant: Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

Inventor： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

IPC: G06F15/00 ,  G06F15/76

CPC classification number: G06F15/8007

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract translation: 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

公开(公告)号：US06789176B2

公开(公告)日：2004-09-07

申请号：US09286332

申请日：1999-04-05

Applicant: Shiro Uriu ,  Masanobu Furukoshi ,  Tetsuaki Wakabayashi ,  Kazumasa Sonoda

Inventor： Shiro Uriu ,  Masanobu Furukoshi ,  Tetsuaki Wakabayashi ,  Kazumasa Sonoda

IPC: G06F1206

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L2012/5681

Abstract: In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.

Abstract translation: 在具有简单布置的公共缓冲装置中，在接收到多地址呼叫时，可以从缓冲存储器高效地释放写入地址。 对于要发送到特定线路的ATM信元，在公共缓冲存储器中设置写入地址，并且将ATM信元写入写入地址。 ATM单元从对应于写入地址的地址读取，并被发送到特定的行。 然后，释放相关的写入地址。 在写入表中输入多个多地址线，在公共缓冲设备中以特定地址写入的ATM信元可以跨多路地址线进行组播。 每当从特定地址读取ATM信元时，将读取控制表中的ATM信元的发送指定行与设置在写入控制表中的多地址线进行比较。 当行匹配时，释放写入控制表中设置的ATM信元的写入地址。

公开(公告)号：US5691977A

公开(公告)日：1997-11-25

申请号：US580534

申请日：1995-12-29

Applicant: Shuji Yoshimura ,  Satoshi Kakuma ,  Masami Murayama ,  Shiro Uriu ,  Tadashi Hoshino

Inventor： Shuji Yoshimura ,  Satoshi Kakuma ,  Masami Murayama ,  Shiro Uriu ,  Tadashi Hoshino

IPC: H04M3/00 ,  H04L12/28 ,  H04L12/70 ,  H04Q3/00 ,  H04Q11/04 ,  H04L12/56

CPC classification number: H04Q11/0478 ,  H04L49/3081 ,  H04L2012/5614 ,  H04L2012/5619

Abstract: In a data access device for writing into or read from a data conversion table on the basis of a clock signal extracted from a cell being transferred over a line, a clock signal generator of the invention generates a second clock signal which differs from the first clock signal extracted from an incoming cell. A write/read control unit writes data into or reads data for maintenance from the data conversion table on the basis of either the first clock signal or the second clock signal when the line is normal. In the event of the occurrence of a failure in the line, on the other hand, the write/read control circuit permits the data conversion table to be written into or read from for maintenance on the basis of the second clock signal.

Abstract translation: 本发明的时钟信号发生器根据从通过线路传输的单元提取的时钟信号写入数据转换表或从数据转换表读取数据存取装置，产生与第一时钟不同的第二时钟信号 从进入的小区提取的信号。 写入/读取控制单元在线路正常时，基于第一时钟信号或第二时钟信号，将数据写入数据转换表或从数据转换表读取数据进行维护。 另一方面，在线路中出现故障的情况下，写入/读取控制电路允许数据转换表基于第二时钟信号写入或读取以进行维护。

公开(公告)号：US5602826A

公开(公告)日：1997-02-11

申请号：US565048

申请日：1995-11-30

Applicant: Shuji Yoshimura ,  Shiro Uriu ,  Satoshi Kakuma

Inventor： Shuji Yoshimura ,  Shiro Uriu ,  Satoshi Kakuma

IPC: H04L12/56 ,  H04Q11/04 ,  H04J3/14

CPC classification number: H04Q11/0478 ,  H04L2012/5628 ,  H04L2012/5652

Abstract: A test system exactly checks the integrity of data in an ATM system, and generates a test cell of a desired band. In the first aspect of the system in which data stored in an ATM cell are transmitted in an 8-bit parallel format in the ATM system, a test cell generating device connected to an input line outputs a test cell having 1 in all of the eight bits or having zero in all of the eight bits, and the test cell confirming device connected to an output line of the ATM switch detects the above described data. In the second aspect, the test cell generating device provided in an input trunk outputs a test cell of a desired band based on a ratio between two optional integers N and n (N.gtoreq.n), the state of a buffer of the ATM switch is monitored, and a load test is conducted to determine whether or not any cell has been destroyed.

Abstract translation: 测试系统精确地检查ATM系统中数据的完整性，并生成所需频段的测试单元。 在ATM系统中以8比特并行格式发送存储在ATM信元中的数据的系统的第一方面中，连接到输入线的测试单元生成装置输出具有1个全部八个的测试单元 位或在所有八位中具有零，并且连接到ATM交换机的输出线的测试单元确认装置检测上述数据。 在第二方面，提供在输入中继线中的测试单元产生装置基于两个可选整数N和n（N> / = n）之间的比率输出所需频带的测试单元，ATM的缓冲器的状态 监控开关，并进行负载测试，以确定任何电池是否已被破坏。

公开(公告)号：US5555265A

公开(公告)日：1996-09-10

申请号：US332379

申请日：1994-10-31

Applicant: Satoshi Kakuma ,  Shiro Uriu ,  Noriko Samejima ,  Kazuo Hajikano

Inventor： Satoshi Kakuma ,  Shiro Uriu ,  Noriko Samejima ,  Kazuo Hajikano

IPC: H04Q3/00 ,  H04L12/813 ,  H04L12/815 ,  H04L12/863 ,  H04L12/911 ,  H04L12/931 ,  H04L12/56

CPC classification number: H04L49/505 ,  H04L12/5693 ,  H04L47/10 ,  H04L47/522 ,  H04L47/6215 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/3081 ,  H04L49/9036 ,  H04L49/9078 ,  H04L2012/5651 ,  H04L2012/5672 ,  H04L2012/5681 ,  H04L49/253 ,  H04L49/30

Abstract: A switching path setting system is disposed between an input line connected to switching equipment and a switch. An input interface device allocates a cell to a quality class as tag information corresponding to an identifier of the cell. A quality class buffer stores the cell corresponding to the quality class allocated by the input interface device corresponding to the quality class. A cell is read from the quality class buffer at a band allocated to each quality class.

Abstract translation: 开关路径设定系统设置在与开关装置连接的输入线与开关之间。 输入接口设备将小区分配给质量类作为与小区的标识符相对应的标签信息。 质量类缓冲器存储与由质量等级对应的由输入接口设备分配的质量等级对应的单元。 在分配给每个质量等级的频带上从质量等级缓冲器读取单元。

公开(公告)号：US5408461A

公开(公告)日：1995-04-18

申请号：US215313

申请日：1994-03-21

Applicant: Shiro Uriu ,  Satoshi Kakuma ,  Shuji Yoshimura

Inventor： Shiro Uriu ,  Satoshi Kakuma ,  Shuji Yoshimura

IPC: H04L29/14 ,  H04L12/70 ,  H04J3/14 ,  H04L1/24 ,  H04L12/26

CPC classification number: H04L49/3009 ,  H04L49/3081 ,  H04L49/309 ,  H04L49/555 ,  H04L2012/5628 ,  H04L49/30

Abstract: An ATM transmission system transmits cell-formatted data in an asynchronous transfer mode, and aims at conducting an online path route test in the system. If one path route only is established in the system, then one or more valid cell detecting units for detecting, upon receipt of a cell enable signal indicating that a valid cell to pass through the path route has been sent, the arrival of a valid cell are provided at an optional point including an ATM switch in the path route so that the path route can be partially or entirely validity-checked. If plurality of valid path routes are established, the system provides, in addition to the valid cell detecting units, a virtual path identifier and virtual channel identifier comparing unit for comparing values of the VPI and VCI stored therein with values of a VPI and a VCI added to an arriving cell, and a path route validity check unit for partially or entirely validity-checking a path route in the ATM transmission system.

Abstract translation: ATM传输系统以异步传输模式发送小区格式数据，目的是在系统中进行在线路径测试。 如果仅在系统中建立一个路径路径，则一个或多个有效的小区检测单元在接收到指示通过路径路由的有效小区的小区启用信号已被发送时，检测有效小区的到达 被提供在包括路由路由中的ATM交换机的可选点处，使得可以部分地或完全地进行有效性检查。 如果建立了多个有效的路径路由，则除了有效的小区检测单元之外，系统还提供虚拟路径标识符和虚拟信道标识符比较单元，用于比较其中存储的VPI和VCI的值与VPI和VCI的值 以及路由有效性检查单元，用于部分或全部有效性地检查ATM传输系统中的路径路径。

公开(公告)号：US5295134A

公开(公告)日：1994-03-15

申请号：US853257

申请日：1992-03-18

Applicant: Shuji Yoshimura ,  Satoshi Kakuma ,  Shiro Uriu ,  Naoyuki Izawa

Inventor： Shuji Yoshimura ,  Satoshi Kakuma ,  Shiro Uriu ,  Naoyuki Izawa

IPC: H04M3/22 ,  H04Q3/545 ,  H04Q11/04 ,  H04L12/26

CPC classification number: H04L12/5601 ,  H04L49/106 ,  H04L49/255 ,  H04L49/3081 ,  H04L49/309 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5681

Abstract: An in-service activator for a broadband exchanger has a dual system structure, in which a first system and a second system form a dual pair. The first system and the second system in the dual pair each has at least one [1] channel converter and a switcher. A channel converter stores channel setting information for use in routing a cell inputted from a line, and outputs the cell inputted from the line by attaching the channel setting information to the cell. The switcher switches a cell outputted from a channel converter. The interfacer stores, in a channel converter of a to-be-activated standby system in the dual pair, the channel setting information read from the corresponding channel converter of an act system in the duplex pair.

Abstract translation: 用于宽带交换机的在线激活器具有双系统结构，其中第一系统和第二系统形成双对。 双对中的第一系统和第二系统每个具有至少一个（1）信道转换器和切换器。 通道转换器存储用于路由从一行输入的单元的通道设置信息，并且通过将通道设置信息附加到该单元来输出从该行输入的单元。 切换器切换从信道转换器输出的单元。 该接口在双对中的待激活待机系统的信道转换器中存储从双工对中的动作系统的相应信道转换器读取的信道设置信息。

公开(公告)号：US07227861B2

公开(公告)日：2007-06-05

申请号：US09805545

申请日：2001-03-13

Applicant: Hiroshi Tomonaga ,  Masakatsu Nagata ,  Kenichi Kawarai ,  Naoki Matsuoka ,  Kenichi Okabe ,  Shiro Uriu

Inventor： Hiroshi Tomonaga ,  Masakatsu Nagata ,  Kenichi Kawarai ,  Naoki Matsuoka ,  Kenichi Okabe ,  Shiro Uriu

IPC: H04L12/56

CPC classification number: H04Q11/0421 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13296

Abstract: Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.

Abstract translation: 从输入HW＃0到＃3输入到分组交换设备的分组被掩埋在时隙A到D中。分组交换设备以时隙为单位交替地切换输入分组，并将分组输入到两个4×4交换机。 4x4交换机进行正常交换，并将数据包分配到相应的输出端口。 然后，在切换之后从两个4×4交换机输出的分组交替复用，并输出到输出HW＃0至＃3。 通过如上所述进行分组的切换，防止了处理开销的增加，并且也可以容易地进行扩展。 此外，硬件规模可以减小。

公开(公告)号：US20060004980A1

公开(公告)日：2006-01-05

申请号：US11034862

申请日：2005-01-14

Applicant: Mitsuharu Wakayoshi ,  Shiro Uriu

Inventor： Mitsuharu Wakayoshi ,  Shiro Uriu

IPC: G06F12/00

CPC classification number: G06F9/3885 ,  G06F9/345 ,  G06F9/3891

Abstract: A plurality of address creators are provided corresponding to a plurality of memories of ALU modules. The address creators create addresses for reading or writing data from the memories each time a connection configuration is switched. In creating addresses in the memories, the address creators enable operations to be set by using various types of parameters and set values by mounting special-purpose hardware for memory ports, so that addresses can be created at high-speed.

Abstract translation: 对应于ALU模块的多个存储器提供多个地址创建者。 每次连接配置切换时，地址创建者创建地址来读取或写入数据。 在创建存储器中的地址时，地址创建者可以通过使用各种类型的参数来设置操作，并通过为存储器端口安装专用硬件设置值，从而可以高速创建地址。

公开(公告)号：US06947413B2

公开(公告)日：2005-09-20

申请号：US09942314

申请日：2001-08-29

Applicant: Tetsuaki Wakabayashi ,  Kenichi Okabe ,  Shiro Uriu ,  Hiroshi Tomonaga ,  Naoki Matsuoka

Inventor： Tetsuaki Wakabayashi ,  Kenichi Okabe ,  Shiro Uriu ,  Hiroshi Tomonaga ,  Naoki Matsuoka

IPC: H04L12/70 ,  H04L12/761 ,  H04L12/931 ,  H04L12/947 ,  H04L12/28

CPC classification number: H04L49/101 ,  H04L49/201 ,  H04L49/25

Abstract: A switching apparatus that is used for high-speed large-capacity routing and a communication apparatus and communication system that are used for an efficient recursive multicast. A matrix switch performs self-routing on a packet on the basis of a tag including output route information set in the packet. Selectors are located so as to correspond to N output ports P#1 through P#N of the matrix switch and perform N-to-one selection control. Setting registers hold selection information used by the selectors to select a signal.

Abstract translation: 用于高速大容量路由的交换装置和用于高效递归组播的通信装置和通信系统。 矩阵开关基于包括在分组中设置的输出路由信息的标签在分组上执行自路由。 选择器被定位成对应于矩阵开关的N个输出端口P＃1到P＃N，并执行N-1选择控制。 设置寄存器保存选择器使用的选择信息来选择一个信号。