公开(公告)号：US20110163831A1

公开(公告)日：2011-07-07

申请号：US13047699

申请日：2011-03-14

申请人： Carol Barrett ,  Tom McKay ,  Subhas Bothra

发明人： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

摘要翻译： 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US07614024B2

公开(公告)日：2009-11-03

申请号：US11244514

申请日：2005-10-06

申请人： Subhas Bothra

发明人： Subhas Bothra

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

摘要： Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.

摘要翻译： 本发明的实施例提供了一种系统和方法，用于在设计期间使用诸如位置和路线工具或布局工具的工具来实现金属填充。 与在设计和布局之后执行金属填充的现有已知解决方案不同，在布局期间，根据要制造的器件的设计规则，均匀地形成导电迹线图案并进行间隔，从而实现更多的规划和设计，进行金属填充。 在设计和布局期间，将导电迹线划分为有源和无源段可以在设计和布局期间识别器件内的关键或敏感器件元件的潜在负面影响。 以前，设计和布局后实施了金属填充，并且经常导致IC设计中以前未考虑的负面影响。 本发明的实施例减少了在设计和布局之后掺入金属填充物的其他装置中的劣化。 另外，因为在IC的设计和布局期间考虑了非活性金属填充段的物理特性。

公开(公告)号：US20060273874A1

公开(公告)日：2006-12-07

申请号：US11504073

申请日：2006-08-15

申请人： Carol Barrett ,  Tom McKay ,  Subhas Bothra

发明人： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

公开(公告)号：US07095307B1

公开(公告)日：2006-08-22

申请号：US10623084

申请日：2003-07-17

申请人： Carol Barrett ,  Tom McKay ,  Subhas Bothra

发明人： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

公开(公告)号：US06492716B1

公开(公告)日：2002-12-10

申请号：US09846335

申请日：2001-04-30

申请人： Subhas Bothra ,  Thomas G. McKay ,  Ravi Jhota

发明人： Subhas Bothra ,  Thomas G. McKay ,  Ravi Jhota

IPC分类号： H01L2302

CPC分类号： H01L23/564 ,  H01L23/552 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate. In this way, the seal ring provides substantially reduced noise coupling among the circuits but still maintains an effective wall around the periphery of the die to protect the circuits against moisture and ionic contamination penetration.

摘要翻译： 本发明的实施例提供了一种密封环，其包括将密封环分隔成密封环部分的多个切口，所述密封环部分邻近集成电路管芯中的不同电路设置。 切割可以通过密封环减少不同电路之间的噪声耦合。 为了进一步将敏感的RF /模拟电路与数字电路产生的噪声隔离开，密封环可能是与基板隔离的电气（用于直流噪声）。 这通过例如在密封环和衬底之间插入多晶硅层和栅极氧化物来实现。 此外，n阱/ p阱电容器可以与栅极氧化物串联形成，例如通过在p型衬底中注入多晶硅层下面的n阱。 以这种方式，密封环在电路之间提供显着降低的噪声耦合，但仍然保持围绕芯片周边的有效壁，以保护电路免受潮湿和离子污染的渗透。

公开(公告)号：US06229685B1

公开(公告)日：2001-05-08

申请号：US09467734

申请日：1999-12-20

申请人： Subhas Bothra ,  Dipankar Pramanik ,  Calvin T. Gabriel

发明人： Subhas Bothra ,  Dipankar Pramanik ,  Calvin T. Gabriel

IPC分类号： H01G4228

CPC分类号： H01L28/60 ,  H01L28/55

摘要： A capacitor and a method of making the capacitor is provided. The capacitor includes a metallization line with a high dielectric constant layer defined over the metallization line. A thin metallization film is defined over the high dielectric constant layer, such that the thin metallization film defines a top plate of the capacitor, the high dielectric constant layer defines a dielectric for the capacitor, and the metallization line defines a bottom plate for the capacitor. The metallization line is defined from a metallization level and the thin metallization film is defined before a next metallization level above the metallization level is defined.

摘要翻译： 提供电容器和制造电容器的方法。 电容器包括金属化线，其具有限定在金属化线上的高介电常数层。 在高介电常数层上限定薄金属化膜，使得薄金属化膜限定电容器的顶板，高介电常数层限定用于电容器的电介质，并且金属化线限定用于电容器的底板 。 金属化线由金属化水平限定，并且在限定金属化水平以上的下一个金属化水平之前限定薄金属化膜。

公开(公告)号：US06221759B1

公开(公告)日：2001-04-24

申请号：US09100639

申请日：1998-06-19

申请人： Subhas Bothra ,  Stephen L. Skala

发明人： Subhas Bothra ,  Stephen L. Skala

IPC分类号： H01L214763

CPC分类号： H01L21/76807

摘要： Disclosed is a method for forming an aligned via under a trench to prevent voiding in a dual damascene process. The trench is formed in an oxide layer that is formed over a first metal layer and the first metal layer is formed over a semiconductor substrate. The method includes forming an etch stop layer over the oxide layer and forming a set of adjacent trenches in the oxide layer through a portion of the etch stop layer. The method also includes forming a resist layer at least partially over the etch stop layer. The resist layer is formed in a via pattern to expose the set of adjacent trenches through the via pattern. The method further includes etching the oxide layer under the set of adjacent trenches until the oxide layer is etched through to expose at least a portion of the first metal layer so as to form a via under each of the adjacent trenches. In this process, the etch stop layer inhibits the oxide layer underneath from being etched substantially such that each of the vias formed under the each of the adjacent trenches is substantially of a same width as and in alignment with the associated trench above.

摘要翻译： 公开了一种用于在沟槽下形成对准的通孔以防止双镶嵌工艺中的空隙的方法。 沟槽形成在形成在第一金属层上的氧化物层中，并且第一金属层形成在半导体衬底上。 该方法包括在氧化物层上形成蚀刻停止层，并通过蚀刻停止层的一部分在氧化物层中形成一组相邻的沟槽。 该方法还包括至少部分地在蚀刻停止层上形成抗蚀剂层。 抗蚀剂层形成为通孔图案，以通过通孔图案露出该组相邻的沟槽。 该方法还包括蚀刻相邻沟槽组之下的氧化物层，直到蚀刻氧化层以露出第一金属层的至少一部分，以便在每个相邻的沟槽下形成通孔。 在该过程中，蚀刻停止层抑制下面的氧化物层被基本蚀刻，使得形成在每个相邻沟槽之下的每个通孔基本上具有与上述相关沟槽相同的宽度和与之相对应的沟槽的对准。

公开(公告)号：US6010939A

公开(公告)日：2000-01-04

申请号：US052865

申请日：1998-03-31

申请人： Subhas Bothra

发明人： Subhas Bothra

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/20

CPC分类号： H01L21/76224 ,  H01L21/763

摘要： Disclosed is a capacitive structure and method for making the capacitive structure for suppressing inductive noise produced by high performance device power supplies. The capacitive structure includes a trench having a bottom surface and respective walls that are integral with the bottom surface. The trench is defined in a semiconductor substrate and is configured to isolate at least one transistor active area from another transistor active area. The structure further includes an oxide layer that is defined along the bottom surface and the respective walls of the trench, such that a channel is defined within the trench between the oxide layer that is defined along the bottom surface and the respective walls. The structure also includes a conductive polysilicon layer that is defined within the channel and is within the trench. The conductive polysilicon layer defines a conductive electrode that is separated from the semiconductor substrate by a thickness of the oxide layer.

摘要翻译： 公开了用于制造用于抑制由高性能器件电源产生的感应噪声的电容结构的电容结构和方法。 电容结构包括具有底表面和与底表面成一体的相应壁的沟槽。 沟槽被限定在半导体衬底中并且被配置为将至少一个晶体管有源区与另一晶体管有源区隔离。 该结构还包括沿着沟槽的底表面和相应壁限定的氧化物层，使得在沿着底表面限定的氧化物层和相应壁之间的沟槽内限定沟道。 该结构还包括限定在沟道内并且在沟槽内的导电多晶硅层。 导电多晶硅层限定了通过氧化物层的厚度与半导体衬底分离的导电电极。

公开(公告)号：US5976987A

公开(公告)日：1999-11-02

申请号：US943839

申请日：1997-10-03

申请人： Ian Robert Harvey ,  Calvin Todd Gabriel ,  Subhas Bothra

发明人： Ian Robert Harvey ,  Calvin Todd Gabriel ,  Subhas Bothra

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76804 ,  H01L21/31116

摘要： A self-aligned contact etch and method for forming a self-aligned contact etch. In one embodiment, the present invention performs an oxide selective etch to form an opening originating at a top surface of a photoresist layer. The opening extends through an underlying oxide layer, and terminates at a top surface of a nitride layer which underlies the oxide layer. Next, the present invention performs a nitride selective etch to extend the opening through the nitride layer to an underlying contact layer. In the present invention, the nitride selective etch causes the photoresist layer to be etched/receded. The nitride selective etch of the present invention further causes the oxide layer to be etched at and near the opening at the interface between the photoresist layer and the oxide layer. As a result, the opening is rounded at the top edge thereof when the layer of photoresist is removed.

摘要翻译： 用于形成自对准接触蚀刻的自对准接触蚀刻和方法。 在一个实施方案中，本发明进行氧化物选择性蚀刻以形成源于光致抗蚀剂层的顶表面的开口。 开口延伸通过下面的氧化物层，并且终止于在氧化物层下面的氮化物层的顶表面。 接下来，本发明进行氮化物选择性蚀刻以将穿过氮化物层的开口延伸到下面的接触层。 在本发明中，氮化物选择性蚀刻使光致抗蚀剂层被蚀刻/后退。 本发明的氮化物选择性蚀刻还使得在光致抗蚀剂层和氧化物层之间的界面处的开口处和附近蚀刻氧化物层。 结果，当去除光致抗蚀剂层时，开口在其顶部边缘处是圆形的。

公开(公告)号：US5913141A

公开(公告)日：1999-06-15

申请号：US134741

申请日：1998-08-14

申请人： Subhas Bothra

发明人： Subhas Bothra

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76876 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927

摘要： Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.