公开(公告)号：US5850090A

公开(公告)日：1998-12-15

申请号：US744677

申请日：1996-11-06

申请人： Toshiyuki Oashi ,  Takahisa Eimori

发明人： Toshiyuki Oashi ,  Takahisa Eimori

IPC分类号： H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/10808

摘要： In a dynamic semiconductor memory device including a thin film SOI/MOSFET having a semiconductor layer on an insulator as an active region, an "L" level potential of a memory cell transistor, which connects/disconnects a capacitor for storing data as electric charges and a bit line for reading/writing data, is set at a fixed value higher than a ground potential and lower than a power supply potential, and a substrate bias is set at the ground potential. Even if isolation is carried out by LOCOS, sub-threshold leakage current due to a parasitic MOS in the vicinity of LOCOS edge can be suppressed because the potential of a word line is lower than that of the bit line when the memory cell transistor is in a cut-off state. Therefore, a dynamic semiconductor memory device including a thin film SOI/MOSFET which is immune to disturbing refresh can be achieved.

摘要翻译： 在包括在绝缘体上具有半导体层的薄膜SOI / MOSFET作为有源区的动态半导体存储器件中，存储单元晶体管的“L”电位电位连接/断开用于存储数据的电容器作为电荷， 用于读/写数据的位线被设置为比接地电位高且低于电源电位的固定值，并且将衬底偏置设置为接地电位。 即使由LOCOS进行隔离，由于在存储单元晶体管处于位置时，由于字线的电位低于位线的电位，所以可以抑制由LOCOS边缘附近的寄生MOS引起的次阈值漏电流 截止状态。 因此，可以实现具有免受干扰刷新的薄膜SOI / MOSFET的动态半导体存储器件。

公开(公告)号：US5721444A

公开(公告)日：1998-02-24

申请号：US824550

申请日：1997-03-25

申请人： Toshiyuki Oashi ,  Jiro Matsufusa ,  Takahisa Eimori ,  Tadashi Nishimura

发明人： Toshiyuki Oashi ,  Jiro Matsufusa ,  Takahisa Eimori ,  Tadashi Nishimura

IPC分类号： H01L21/316 ,  H01L21/02 ,  H01L21/205 ,  H01L21/265 ,  H01L21/76 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/78606 ,  H01L29/78609

摘要： A buried insulating layer is provided in a semiconductor substrate, in a position separated from its major surface. A LOCOS isolation film is provided in the major surface of the semiconductor substrate for isolating an active region from other active regions. A thin-film transistor is provided in the active region. The thin-film transistor comprises a gate electrode which is provided on the active region with interposition of a gate insulating layer. A pair of source/drain layers are provided in the major surface of the semiconductor substrate on both sides of the gate electrode. A high-concentration impurity layer is provided in the semiconductor substrate immediately under the buried insulating layer.

摘要翻译： 掩埋绝缘层设置在半导体衬底中的与其主表面分离的位置。 在半导体衬底的主表面上提供了一个LOCOS隔离膜，用于将活性区域与其它活性区域隔离。 在有源区域中设置薄膜晶体管。 薄膜晶体管包括设置在有源区上的栅极，插入栅极绝缘层。 在栅电极的两侧的半导体衬底的主表面上设置一对源极/漏极层。 在掩埋绝缘层正下方的半导体衬底中设置高浓度杂质层。

公开(公告)号：US09054103B2

公开(公告)日：2015-06-09

申请号：US14112926

申请日：2012-03-26

申请人： Kazuo Tomita ,  Toshiyuki Oashi ,  Hidenori Sato

发明人： Kazuo Tomita ,  Toshiyuki Oashi ,  Hidenori Sato

IPC分类号： H01L23/52 ,  H01L27/02 ,  H01L21/8238

CPC分类号： H01L29/0696 ,  H01L21/823871 ,  H01L23/52 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/1095 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate interconnection portion includes a first gate interconnection portion, a second gate interconnection portion, and a third gate interconnection portion. The first gate interconnection portion is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region. The second gate interconnection portion is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion toward the power supply interconnection, and extends across a boundary between the element formation region and an element isolation insulating film, which is in parallel to an X axis direction. The third gate interconnection portion further extends in parallel to the Y-axis direction from the second gate interconnection portion toward the power supply interconnection.

摘要翻译： 栅极互连部分包括第一栅极互连部分，第二栅极互连部分和第三栅极互连部分。 第一栅极互连部分形成为平行于Y轴方向朝向电源互连并延伸到元件形成区域内的规定位置。 第二栅极互连部分形成为平行于从第一栅极互连部分朝向电源互连方向相对于Y轴方向倾斜弯曲的方向，并延伸穿过元件形成区域和元件隔离绝缘膜之间的边界 ，它与X轴方向平行。 第三栅极互连部分还从第二栅极互连部分向电源互连方向平行于Y轴方向延伸。

公开(公告)号：US06677193B2

公开(公告)日：2004-01-13

申请号：US10255619

申请日：2002-09-27

申请人： Toshiyuki Oashi

发明人： Toshiyuki Oashi

IPC分类号： H01L21336

CPC分类号： H01L21/743 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/66772

摘要： A method of producing a semiconductor device having an SOI transistor and a multi-layer wiring, including: preparing a silicon substrate having a front face and a back face; forming an inter-layer insulation layer on the front face of the silicon substrate; forming a multi-layer wiring in the inter-layer insulation layer; fixing a substrate on the inter-layer insulation layer; thinning the silicon substrate from the back face into a thin film so that the silicon substrate becomes an SOI layer; and forming a channel layer and a gate electrode on a back of the channel layer in the SOI layer, and further forming a source and a drain facing each other having the channel layer in between so that an SOI transistor is obtained.

摘要翻译： 一种制造具有SOI晶体管和多层布线的半导体器件的方法，包括：制备具有正面和背面的硅衬底; 在所述硅衬底的前表面上形成层间绝缘层; 在层间绝缘层中形成多层布线; 将衬底固定在层间绝缘层上; 将硅衬底从背面细化成薄膜，使得硅衬底变成SOI层; 以及在SOI层的沟道层的背面形成沟道层和栅电极，并且进一步形成相互面对的具有沟道层的源极和漏极，从而获得SOI晶体管。

公开(公告)号：US06424041B1

公开(公告)日：2002-07-23

申请号：US09848207

申请日：2001-05-04

申请人： Toshiyuki Oashi ,  Takashi Uehara

发明人： Toshiyuki Oashi ,  Takashi Uehara

IPC分类号： H01L2348

CPC分类号： H01L27/10882 ,  H01L23/53228 ,  H01L27/10814 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having copper wiring and capable of reliably preventing copper atoms from diffusing into a memory storage region even in a slight amount is obtained. This semiconductor device includes on a semiconductor substrate a memory cell portion and a wiring portion including copper wires, and includes in a region surrounding the memory cell portion a copper-diffusion preventing film for blocking diffusion of copper atoms from the wiring portion.

摘要翻译： 可以获得具有铜布线并且能够可靠地防止铜原子甚至少量扩散到存储器存储区域中的半导体器件。 该半导体装置在半导体基板上包括存储单元部分和包括铜线的布线部分，并且在包围存储单元部分的区域中包括用于阻挡铜原子从布线部分扩散的铜扩散防止膜。

公开(公告)号：US06890817B2

公开(公告)日：2005-05-10

申请号：US10633576

申请日：2003-08-05

申请人： Hiroshi Maeda ,  Toshiyuki Oashi ,  Takashi Uehara

发明人： Hiroshi Maeda ,  Toshiyuki Oashi ,  Takashi Uehara

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894

摘要： A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

摘要翻译： 可以获得半导体器件及其制造方法，其中可以防止缺陷的发生，并且可以降低制造成本。 半导体器件包括电容器电极，绝缘层和布线层。 电容器电极形成在半导体衬底上。 形成在电容器电极上的绝缘膜具有露出电容器电极的一部分并具有上表面的沟槽。 布线层填充在沟槽的内部，具有上表面并与电容器电极连接。 布线层的上表面位于与绝缘膜的上表面大致相同的平面上。

公开(公告)号：US06630705B2

公开(公告)日：2003-10-07

申请号：US09903735

申请日：2001-07-13

申请人： Hiroshi Maeda ,  Toshiyuki Oashi ,  Takashi Uehara

发明人： Hiroshi Maeda ,  Toshiyuki Oashi ,  Takashi Uehara

IPC分类号： H01L27108

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894

摘要： A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

摘要翻译： 可以获得半导体器件及其制造方法，其中可以防止缺陷的发生，并且可以降低制造成本。 半导体器件包括电容器电极，绝缘层和布线层。 电容器电极形成在半导体衬底上。 形成在电容器电极上的绝缘膜具有露出电容器电极的一部分并具有上表面的沟槽。 布线层填充在沟槽的内部，具有上表面并与电容器电极连接。 布线层的上表面位于与绝缘膜的上表面大致相同的平面上。

公开(公告)号：US06770930B2

公开(公告)日：2004-08-03

申请号：US10369636

申请日：2003-02-21

申请人： Toshiyuki Oashi

发明人： Toshiyuki Oashi

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object to provide a semiconductor device in which a structure of a capacitor is simplified. Any electrical connection of a capacitor (CP10) and source—drain regions (11) and (13) is carried out by a contact plug (101) inserted in the capacitor (CP10) and reaching the source—drain regions (11) and (13). The capacitor (CP10) has a capacitor upper electrode (103) provided to be embedded in an upper main surface of an interlayer insulating film (3) and a capacitor dielectric film (102) provided to cover a side surface and a lower surface of the capacitor upper electrode (103). Moreover, the capacitor dielectric film (102) is also provided to cover a side surface of the contact plug (101) formed to penetrate through the capacitor upper electrode (103), and a portion of the contact plug (101) which is covered with the capacitor dielectric film (102) functions as the capacitor lower electrode (101).

摘要翻译： 本发明的目的是提供一种简化了电容器结构的半导体器件。 电容器（CP10）和源极 - 漏极区域（11）和（13）的任何电连接由插入到电容器（CP10）中的接触插头（101）进行并到达源极 - 漏极区域（11）和 13）。 电容器（CP10）具有设置成嵌入在层间绝缘膜（3）的上主表面中的电容器上电极（103）和设置成覆盖层间绝缘膜（3）的侧表面和下表面的电容器电介质膜 电容器上电极（103）。 此外，还设置电容器电介质膜（102）以覆盖形成为穿过电容器上电极（103）的接触插塞（101）的侧表面，以及覆盖有接触插塞（101）的部分 电容器电介质膜（102）用作电容器下电极（101）。

公开(公告)号：US5654573A

公开(公告)日：1997-08-05

申请号：US740511

申请日：1996-10-30

申请人： Toshiyuki Oashi ,  Takahisa Eimori

发明人： Toshiyuki Oashi ,  Takahisa Eimori

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78648

摘要： A semiconductor device having an SOI structure which involves no parasitic MOS transistor and substrate floating effect and has a planar element isolation region and, a manufacturing method therefor. In the semiconductor device, a field shield gate composed of an oxide film and a field shield gate electrode is formed to be buried under an SOI layer. As a result, it is possible to prevent generation of a parasitic transistor and substrate floating effects inherent in field shield gate while obtaining a planar element isolation structure.

摘要翻译： 具有SOI结构的半导体器件，其不具有寄生MOS晶体管和衬底浮置效应，并且具有平面元件隔离区域及其制造方法。 在半导体装置中，形成由氧化物膜和场屏蔽栅电极构成的场屏蔽栅极，埋设在SOI层的下方。 结果，可以在获得平面元件隔离结构的同时防止在场屏蔽栅极中固有的寄生晶体管和衬底浮置效应的产生。

公开(公告)号：US20140043063A1

公开(公告)日：2014-02-13

申请号：US14112926

申请日：2012-03-26

申请人： Kazuo Tomita ,  Toshiyuki Oashi ,  Hidenori Sato

发明人： Kazuo Tomita ,  Toshiyuki Oashi ,  Hidenori Sato

IPC分类号： H01L23/52

CPC分类号： H01L29/0696 ,  H01L21/823871 ,  H01L23/52 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/1095 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate interconnection portion includes a first gate interconnection portion, a second gate interconnection portion, and a third gate interconnection portion. The first gate interconnection portion is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region. The second gate interconnection portion is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion toward the power supply interconnection, and extends across a boundary between the element formation region and an element isolation insulating film, which is in parallel to an X axis direction. The third gate interconnection portion further extends in parallel to the Y-axis direction from the second gate interconnection portion toward the power supply interconnection.

摘要翻译： 栅极互连部分包括第一栅极互连部分，第二栅极互连部分和第三栅极互连部分。 第一栅极互连部分形成为平行于Y轴方向朝向电源互连并延伸到元件形成区域内的规定位置。 第二栅极互连部分形成为平行于从第一栅极互连部分朝向电源互连方向相对于Y轴方向倾斜弯曲的方向，并延伸穿过元件形成区域和元件隔离绝缘膜之间的边界 ，它与X轴方向平行。 第三栅极互连部分还从第二栅极互连部分向电源互连方向平行于Y轴方向延伸。