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    Method of manufacturing a semiconductor device with capacitor electrodes
    1.
    发明授权
    Method of manufacturing a semiconductor device with capacitor electrodes 失效
    制造具有电容器电极的半导体器件的方法

    公开(公告)号：US06890817B2

    公开(公告)日：2005-05-10

    申请号：US10633576

    申请日：2003-08-05

    申请人： Hiroshi Maeda ,  Toshiyuki Oashi ,  Takashi Uehara

    发明人： Hiroshi Maeda ,  Toshiyuki Oashi ,  Takashi Uehara

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894

    摘要： A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

    摘要翻译： 可以获得半导体器件及其制造方法，其中可以防止缺陷的发生，并且可以降低制造成本。 半导体器件包括电容器电极，绝缘层和布线层。 电容器电极形成在半导体衬底上。 形成在电容器电极上的绝缘膜具有露出电容器电极的一部分并具有上表面的沟槽。 布线层填充在沟槽的内部，具有上表面并与电容器电极连接。 布线层的上表面位于与绝缘膜的上表面大致相同的平面上。

    Semiconductor device with capacitor electrodes
    2.
    发明授权
    Semiconductor device with capacitor electrodes 失效
    具有电容器电极的半导体器件

    公开(公告)号：US06630705B2

    公开(公告)日：2003-10-07

    申请号：US09903735

    申请日：2001-07-13

    申请人： Hiroshi Maeda ,  Toshiyuki Oashi ,  Takashi Uehara

    发明人： Hiroshi Maeda ,  Toshiyuki Oashi ,  Takashi Uehara

    IPC分类号： H01L27108

    CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894

    摘要： A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

    摘要翻译： 可以获得半导体器件及其制造方法，其中可以防止缺陷的发生，并且可以降低制造成本。 半导体器件包括电容器电极，绝缘层和布线层。 电容器电极形成在半导体衬底上。 形成在电容器电极上的绝缘膜具有露出电容器电极的一部分并具有上表面的沟槽。 布线层填充在沟槽的内部，具有上表面并与电容器电极连接。 布线层的上表面位于与绝缘膜的上表面大致相同的平面上。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06424041B1

    公开(公告)日：2002-07-23

    申请号：US09848207

    申请日：2001-05-04

    申请人： Toshiyuki Oashi ,  Takashi Uehara

    发明人： Toshiyuki Oashi ,  Takashi Uehara

    IPC分类号： H01L2348

    CPC分类号： H01L27/10882 ,  H01L23/53228 ,  H01L27/10814 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having copper wiring and capable of reliably preventing copper atoms from diffusing into a memory storage region even in a slight amount is obtained. This semiconductor device includes on a semiconductor substrate a memory cell portion and a wiring portion including copper wires, and includes in a region surrounding the memory cell portion a copper-diffusion preventing film for blocking diffusion of copper atoms from the wiring portion.

    摘要翻译： 可以获得具有铜布线并且能够可靠地防止铜原子甚至少量扩散到存储器存储区域中的半导体器件。 该半导体装置在半导体基板上包括存储单元部分和包括铜线的布线部分，并且在包围存储单元部分的区域中包括用于阻挡铜原子从布线部分扩散的铜扩散防止膜。

    Semiconductor memory device and semiconductor device
    4.
    发明申请
    Semiconductor memory device and semiconductor device 失效
    半导体存储器件和半导体器件

    公开(公告)号：US20070274139A1

    公开(公告)日：2007-11-29

    申请号：US11826751

    申请日：2007-07-18

    申请人： Masahiro Yamashita ,  Takashi Uehara ,  Mamoru Takaku ,  Hiroaki Nambu

    发明人： Masahiro Yamashita ,  Takashi Uehara ,  Mamoru Takaku ,  Hiroaki Nambu

    IPC分类号： G11C5/14

    CPC分类号： G11C29/023 ,  G11C11/41 ,  G11C29/02 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028

    摘要： A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.

    摘要翻译： 提供了能够通过修整半导体器件的内部特性来提高产量的技术。 半导体器件具有内部降压电路和其特性值（内部电压等）可变的内部升压电路，熔丝电路单元，输入并保持来自外部的信号的JTAG功能单元304 控制电路，其基于熔丝电路单元的输出信号和JTAG功能单元的输出信号进行逻辑运算，并且控制内部降压电路和内部升压电路的特性值 基于控制电路的逻辑运算的结果。

    Method of manufacturing a semiconductor device using a trench isolation technique
    5.
    发明授权
    Method of manufacturing a semiconductor device using a trench isolation technique 失效
    使用沟槽隔离技术制造半导体器件的方法

    公开(公告)号：US6143626A

    公开(公告)日：2000-11-07

    申请号：US330068

    申请日：1999-06-11

    申请人： Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Takashi Nakabayashi

    发明人： Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Takashi Nakabayashi

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76229

    摘要： On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions. Thus, in a highly integrated semiconductor device having a trench isolation, degradation of reliability resulting from the opening of the void in the surface of isolation is prevented.

    摘要翻译： 在半导体衬底上依次沉积二氧化硅膜和氮化硅膜。 使用具有对应于隔离区域的开口的光致抗蚀剂膜，依次蚀刻氮化硅膜，二氧化硅膜和半导体衬底，从而形成沟槽。 在沉积防扩散膜之后，沉积具有可回流性的用于隔离的绝缘膜。 虽然在隔离区域中用于隔离的绝缘膜中形成空隙，但是使用于隔离的绝缘膜回流，从而消除空隙。 之后，通过CMP对整个基板进行平坦化，以除去氮化硅膜和二氧化硅膜，然后在各个元件形成区域中形成栅极绝缘膜，栅极电极，侧壁和源极/漏极区域。 因此，在具有沟槽隔离的高度集成的半导体器件中，防止了由于隔离表面中的空隙的打开引起的可靠性降低。

    Semiconductor apparatus having an n-channel MOS transistor and a p-channel MOS transistor and method for manufacturing the semiconductor apparatus
    6.
    发明授权
    Semiconductor apparatus having an n-channel MOS transistor and a p-channel MOS transistor and method for manufacturing the semiconductor apparatus 失效
    具有n沟道MOS晶体管和p沟道MOS晶体管的半导体装置及其制造方法

    公开(公告)号：US5498908A

    公开(公告)日：1996-03-12

    申请号：US380460

    申请日：1995-01-30

    申请人： Takashi Nakabayashi ,  Takashi Uehara ,  Akihira Shinohara

    发明人： Takashi Nakabayashi ,  Takashi Uehara ,  Akihira Shinohara

    IPC分类号： H01L21/8238 ,  H01L29/49 ,  H01L29/76 ,  H01L23/48

    CPC分类号： H01L21/823842 ,  H01L21/823871 ,  H01L29/4933

    摘要： A semiconductor apparatus with MOS transistors for transmitting electrons from an n type source layer to an n type drain layer through a first channel region in an n-channel MOS transistor and transmitting holes from a p type source layer to a p type drain layer through a second channel region in a p-channel MOS transistor consists of a field oxide layer for separating the n-channel MOS transistor from the p-channel MOS transistor, an n type gate electrode mounted on a first gate oxide film arranged on the first channel region, a p type gate electrode mounted on a second gate oxide film arranged on the second channel region and positioned far away from the n type gate electrode to prevent impurities implanted into one of tile gate electrodes from diffusing into the other gate electrode, and a gate metal wiring connecting the gate electrodes through a gate contact hole to miniaturize the transistors.

    摘要翻译： 一种具有MOS晶体管的半导体器件，用于通过n沟道MOS晶体管中的第一沟道区将电子从n型源极层传输到n型漏极层，并且通过第二沟道将空穴从ap型源极层传输到ap型漏极层 p沟道MOS晶体管的区域由用于从p沟道MOS晶体管分离n沟道MOS晶体管的场氧化物层，安装在布置在第一沟道区上的第一栅氧化膜上的n型栅电极， 型栅电极，其安装在布置在第二沟道区上并位于远离n型栅电极的第二栅极氧化膜上，以防止注入到一块瓦栅电极中的杂质扩散到另一栅电极中;栅极金属布线连接 栅极通过栅极接触孔使晶体管小型化。

    IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF
    10.
    发明申请
    IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF 有权
    图像形成装置及其控制方法

    公开(公告)号：US20090060558A1

    公开(公告)日：2009-03-05

    申请号：US12199426

    申请日：2008-08-27

    申请人： Takashi Uehara

    发明人： Takashi Uehara

    IPC分类号： G03G15/00

    CPC分类号： G03G15/5004

    摘要： An image forming apparatus which is capable of reducing the number of times a second member is separated from a first member upon entry into power-save mode, thereby minimizing failures of a separation unit. A pressure-roller separating mechanism is provided so as to abut and separate a pressure roller and a fixing roller against/from each other. The image forming apparatus is controlled to change to a power-save mode in which power consumption of the image forming apparatus is reduced. The pressure-roller separating mechanism is controlled to separate the pressure roller and the fixing roller from each other in the power-save mode based on a measurement result measured by a timer, and the power-save mode is maintained after the pressure roller and the fixing roller are separated from each other.

    摘要翻译： 一种图像形成装置，其能够减少在进入省电模式时第二构件与第一构件分离的次数，从而使分离单元的故障最小化。 压辊分离机构设置成抵靠和分离加压辊和定影辊。 控制图像形成装置转换成图像形成装置的功耗降低的省电模式。 根据由定时器测量的测量结果，压力辊分离机构被控制为在节电模式下将压力辊和定影辊彼此分开，并且在压力辊和 定影辊彼此分离。