公开(公告)号：US5428236A

公开(公告)日：1995-06-27

申请号：US857727

申请日：1992-03-26

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： Disclosed is a memory having a p-type semiconductor substrate having a high impurity concentration a p-type semiconductor layer is formed on thereof; a groove which is formed so as to extend from a surface of the semiconductor layer to a position inside the semiconductor substrate; an impurity diffused region which is formed on portions of the semiconductor layer and the semiconductor substrate which define the groove; and an electrode which is formed from the groove to level at least above an opening of the groove through capacitor insulation film, the impurity diffused region, capacitor insulation film and electrode constituting trenched capacitor in which the electrode serves first capacitor electrode and the impurity diffused region serves as a second capacitor electrode.

摘要翻译： 公开了具有杂质浓度高的p型半导体衬底的存储器，其上形成有p型半导体层; 形成为从半导体层的表面延伸到半导体衬底内的位置的槽; 形成在限定所述沟槽的所述半导体层和所述半导体衬底的部分上的杂质扩散区域; 以及由沟槽形成的电极，通过电容绝缘膜，杂质扩散区域，电容器绝缘膜和构成沟槽电容器的电极的至少在沟槽的上方平坦化，其中电极用作第一电容器电极和杂质扩散区域 用作第二电容器电极。

公开(公告)号：US4970688A

公开(公告)日：1990-11-13

申请号：US397837

申请日：1989-08-24

申请人： Tsutomu Minagawa ,  Naoyuki Kai ,  Masahide Ohhashi ,  Yukimasa Uchida

发明人： Tsutomu Minagawa ,  Naoyuki Kai ,  Masahide Ohhashi ,  Yukimasa Uchida

IPC分类号： G06F12/00 ,  G06F7/00 ,  G06F17/16 ,  G06T1/20

CPC分类号： G06F7/00

摘要： A memory device having an operating function includes a memory cell array, a register, and a logical opeation circuit. The memory cell array has memory cells arranged in a matrix form of m rows .times.n columns. Data readout or write-in operation with respect to the memory cell array is effected in the unit of n bits of one row. The register has a bit width corresponding to one row of the memory cell array. Data of one row is read out from the memory cell array and is processed by the logical operation circuit together with data stored in the register. The result of operation is written into a desired row of the memory cell array. The memory cell array, register, and logical operation circuit are formed in the same integrated circuit, thus permitting processing such as picture element processing to be effected inside the integrated circuit, without the need to use an external data bus.

摘要翻译： 具有操作功能的存储器件包括存储单元阵列，寄存器和逻辑运算电路。 存储单元阵列具有以m行×n列的矩阵形式排列的存储单元。 相对于存储单元阵列的数据读出或写入操作以一行的n位为单位进行。 寄存器具有对应于存储单元阵列的一行的位宽度。 一行的数据从存储单元阵列中读出，并由逻辑运算电路与存储在寄存器中的数据一起处理。 操作结果写入存储单元阵列的所需行。 存储单元阵列，寄存器和逻辑运算电路形成在相同的集成电路中，从而允许在集成电路内实现诸如图像元素处理的处理，而不需要使用外部数据总线。

公开(公告)号：US4794571A

公开(公告)日：1988-12-27

申请号：US143204

申请日：1988-01-11

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： G11C11/409 ,  G11C11/407 ,  G11C11/4094 ,  G11C11/24

CPC分类号： G11C11/4094

摘要： A dynamic read-write random access memory (DRAM) including a memory cell, a word line and a bit line. The memory cell has a capacitor and a MOS transistor which has a gate connected to the word line, a drain terminal connected to the capacitor and a source terminal connected to the bit line. The DRAM further includes a supply circuit for applying to the bit line a voltage level having a value between the voltage level of the word line and the voltage level of the drain terminal of the MOS transistor when the memory cell is not selected, so as to prevent leakage current from flowing through the MOS transistor.

摘要翻译： 包括存储单元，字线和位线的动态读写随机存取存储器（DRAM）。 存储单元具有电容器和MOS晶体管，其具有连接到字线的栅极，连接到电容器的漏极端子和连接到位线的源极端子。 DRAM还包括供电电路，用于当未选择存储单元时向位线施加具有字线的电压电平和MOS晶体管的漏极端子的电压电平之间的值的电压电平，以便 防止漏电流流过MOS晶体管。

公开(公告)号：US4287574A

公开(公告)日：1981-09-01

申请号：US070394

申请日：1979-08-28

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： G11C14/00 ,  G11C11/40

CPC分类号： G11C14/00 ,  Y10S257/903

摘要： A non-volatile memory cell has a pair of inverter circuits. In each inverter circuit, first and second insulated gate transistors of the first channel type and a third insulated gate transistor of the second channel type are serially connected in this order. The gates of the first transistor and the third transistor are commonly connected each other thereby to form an input terminal. A control terminal is formed at the gate of the second transistor. An output terminal is formed at either the source or the drain of the second transistor. The input terminal of one of the inverter is connected to the output terminal of the other inverter, while the output terminal of the former, to the input terminal of the latter. The control terminal is connected to a common control terminal. In this way, a complementary bistable circuit is formed. Non-volatile memory elements are connected to the connection points between the first and second transistors, respectively.

摘要翻译： 非易失性存储单元具有一对反相器电路。 在每个逆变器电路中，第一通道类型的第一和第二绝缘栅晶体管和第二通道类型的第三绝缘栅极晶体管按此顺序串联连接。 第一晶体管和第三晶体管的栅极共同连接，从而形成输入端。 控制端子形成在第二晶体管的栅极处。 输出端子形成在第二晶体管的源极或漏极的两端。 一个逆变器的输入端子连接到另一个逆变器的输出端子，而前者的输出端子连接到后者的输入端子。 控制端子连接到公共控制端子。 以这种方式，形成互补的双稳态电路。 非易失性存储元件分别连接到第一和第二晶体管之间的连接点。

公开(公告)号：US4123771A

公开(公告)日：1978-10-31

申请号：US705561

申请日：1976-07-15

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34 ,  H03K5/00

CPC分类号： H01L29/792 ,  G11C16/0466

摘要： A nonvolatile semiconductor memory having an insulated gate field effect transistor whose structure is so made as to permit, during the write operation, a substrate surface region below the gate to be substantially enclosed by depletion layers extended from the source and drain regions or by said depletion layers and a channel formed between said regions, thereby increasing a resistance between the substrate and said substrate surface region to decrease the writing current in amount and the writing voltage in level.

摘要翻译： 一种具有绝缘栅场效应晶体管的非易失性半导体存储器，其结构使得在写入操作期间允许栅极下面的衬底表面区域被从源极和漏极区域延伸的耗尽层基本包围，或者通过所述耗尽 层和形成在所述区域之间的通道，从而增加衬底和所述衬底表面区域之间的电阻，以降低写入电流的量和写入电压。

公开(公告)号：US4044343A

公开(公告)日：1977-08-23

申请号：US681557

申请日：1976-04-29

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： G11C14/00 ,  G11C11/40

CPC分类号： G11C14/00

摘要： A non-volatile random access memory system includes a memory array circuit having a plurality of unit non-volatile memory cells arranged in a matrix array. Each unit memory cell includes a flip-flop circuit and two MNOS transistors into which a data in the flip-flop is written and from which the data written therein is transferred to the flip-flop. The system also includes means for selecting a desired one of the unit memory cells and an input-output circuit adapted to supply a data to the selected unit cell and deliver the data read out of the selected unit cell. The system further includes a source voltage variation detector circuit adapted to deliver, when the source voltage for the memory array circuit is rendered ON, a control signal including a readout signal for reading the data in the MNOS transistors into the flip-flop or a source voltage variation detector circuit adapted to generate a control signal including a write signal for writing a data in the flip-flop circuit into the MNOS transistors when the source voltage is rendered OFF and a readout signal for reading the data in the MNOS transistors into the flip-flop circuit when the source voltage is rendered ON, and means for interrupting in synchronism with the control signal a data transfer path between the selected unit memory cell and the input-output circuit so as to prevent any influence from an external circuit when a data transfer is effected between the flip-flop circuit and the MNOS transistors.

摘要翻译： 非易失性随机存取存储器系统包括具有以矩阵阵列排列的多个单位非易失性存储单元的存储器阵列电路。 每个单元存储单元包括触发器电路和两个MNOS晶体管，触发器中的数据被写入其中，并将写入其中的数据从其中传送到触发器。 该系统还包括用于选择单元存储单元中期望的单元存储单元的装置和适于将数据提供给所选单位单元并输送从所选单位单元读出的数据的输入 - 输出电路。 该系统进一步包括源电压变化检测器电路，适于在存储器阵列电路的源极电压为ON时传送包括用于将MNOS晶体管中的数据读入触发器或源极的读出信号的控制信号 电压变化检测器电路，其适于产生包括用于在源电压为OFF时将触发器电路中的数据写入MNOS晶体管的写信号的控制信号，以及用于将MNOS晶体管中的数据读取到翻转中的读出信号 当电源电压为ON时的开关电路，以及用于与所述控制信号同步地中断所选择的单元存储单元和所述输入 - 输出电路之间的数据传输路径的装置，以防止当数据 在触发器电路和MNOS晶体管之间进行传输。

公开(公告)号：US3950737A

公开(公告)日：1976-04-13

申请号：US509490

申请日：1974-09-26

申请人： Yukimasa Uchida ,  Isao Nojima ,  Yoshiaki Matsuno

发明人： Yukimasa Uchida ,  Isao Nojima ,  Yoshiaki Matsuno

IPC分类号： G11C14/00 ,  H03K3/356 ,  H03K5/153 ,  H03K21/00 ,  H03K21/02 ,  H03K21/40 ,  H03K23/52 ,  H03K23/54 ,  G11C11/40 ,  G11C13/00

CPC分类号： H03K5/153 ,  H03K21/02 ,  H03K21/403 ,  H03K3/356008

摘要： A nonvolatile counter circuit is disclosed which includes a nonvolatile insulated gate type field effect memory transistor interposed between the load and active elements of a flip-flop circuit. A switching element is connected in parallel with the memory transistor and a circuit is provided for returning information stored in the nonvolatile memory transistor to the flip-flop after the circuit power source has been turned on. A circuit is also provided for erasing the information stored in the nonvolatile memory transistor. A circuit element is provided for short-circuiting the switching element, and a circuit is provided for writing the information stored in the flip-flop circuit into the nonvolatile memory transistor at the transient of switching off the power.

公开(公告)号：US4641165A

公开(公告)日：1987-02-03

申请号：US475554

申请日：1983-03-15

申请人： Tetsuya Iizuka ,  Syuso Fujii ,  Yukimasa Uchida

发明人： Tetsuya Iizuka ,  Syuso Fujii ,  Yukimasa Uchida

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L27/14

CPC分类号： G11C11/404 ,  H01L27/10805

摘要： The dynamic memory device of the present invention is formed on an integrated semiconductor substrate subjected to alpha radiation and comprises a switching transistor having a switching terminal, an input-output terminal and a memory terminal; a bit line couple to said input-output terminal for supplying a charge to said transistor; a word line coupled to said switching terminal for controlling the switching of said transistor; and, an R-C circuit coupled to the memory terminal and comprising a charge storage capacitor for storing the charge supplied from said bit line and for substantially preventing loss of the stored charge due to particle radiation.

摘要翻译： 本发明的动态存储器件形成在经受α辐射的集成半导体衬底上，并且包括具有开关端子，输入输出端子和存储器端子的开关晶体管; 位线耦合到所述输入输出端子，用于向所述晶体管提供电荷; 耦合到所述开关端子用于控制所述晶体管的开关的字线; 以及R-C电路，其耦合到存储器端子并且包括用于存储从所述位线提供的电荷的电荷存储电容器，并且用于基本上防止由于粒子辐射引起的存储电荷的损失。

公开(公告)号：US4489339A

公开(公告)日：1984-12-18

申请号：US551186

申请日：1983-11-14

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： H01L21/331 ,  H01L27/12 ,  H01L29/73 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/78 ,  H01L29/78612

摘要： A MOS type semiconductor device effectively supplying potential to a substrate region under the channel forming region of the MOS transistor on an insulating substrate. The potential is supplied to the one conductivity type substrate region under the channel forming region which is provided on an insulating substrate and has an extended portion extending in the channel length direction, through a substrate potential take-out region of one conductivity type connecting to the extended substrate. A gate electrode with an extended gate portion is formed on the substrate region through a gate insulating film, so as to cover the substrate region.

摘要翻译： 一种在绝缘基板上有效地向MOS晶体管的沟道形成区域下方的衬底区域提供电位的MOS型半导体器件。 电位被提供给设置在绝缘基板上的沟道形成区域下方的一个导电型基板区域，并且具有沿着沟道长度方向延伸的延伸部分，通过一个导电类型的基板电位取出区域连接到 延长基板。 具有延伸栅极部分的栅电极通过栅极绝缘膜形成在衬底区域上，以覆盖衬底区域。

公开(公告)号：US4467452A

公开(公告)日：1984-08-21

申请号：US331066

申请日：1981-12-15

申请人： Shozo Saito ,  Yukimasa Uchida ,  Kazuhiko Hashimoto ,  Norio Endo

发明人： Shozo Saito ,  Yukimasa Uchida ,  Kazuhiko Hashimoto ,  Norio Endo

IPC分类号： H01L29/792 ,  G11C11/40 ,  H01L29/78

CPC分类号： H01L29/792

摘要： A nonvolatile semiconductor memory device having a gate insulating film with a memory function. An impurity layer having the same conductivity type as that of the substrate region is formed in that substrate region, underlying the gate insulating film having a memory function, in which a channel is formed. The impurity layer has an impurity profile in which a peak of an impurity concentration is in the region distanced by 500 .ANG. or less from the surface of the substrate region and the impurity concentration is 1.times.10.sup.18 cm.sup.-3 or less in the region at the depth of 500 .ANG. or more.

摘要翻译： 一种具有具有记忆功能的栅极绝缘膜的非易失性半导体存储器件。 在其中形成沟道的具有记忆功能的栅极绝缘膜下方的衬底区域中形成具有与衬底区域相同的导电类型的杂质层。 杂质层具有杂质浓度在距离衬底区域的表面远离500或更小的区域中的杂质分布，并且在深度的区域中杂质浓度为1×10 18 cm -3或更小 500 ANGSTROM以上。