公开(公告)号：US3950737A

公开(公告)日：1976-04-13

申请号：US509490

申请日：1974-09-26

申请人： Yukimasa Uchida ,  Isao Nojima ,  Yoshiaki Matsuno

发明人： Yukimasa Uchida ,  Isao Nojima ,  Yoshiaki Matsuno

IPC分类号： G11C14/00 ,  H03K3/356 ,  H03K5/153 ,  H03K21/00 ,  H03K21/02 ,  H03K21/40 ,  H03K23/52 ,  H03K23/54 ,  G11C11/40 ,  G11C13/00

CPC分类号： H03K5/153 ,  H03K21/02 ,  H03K21/403 ,  H03K3/356008

摘要： A nonvolatile counter circuit is disclosed which includes a nonvolatile insulated gate type field effect memory transistor interposed between the load and active elements of a flip-flop circuit. A switching element is connected in parallel with the memory transistor and a circuit is provided for returning information stored in the nonvolatile memory transistor to the flip-flop after the circuit power source has been turned on. A circuit is also provided for erasing the information stored in the nonvolatile memory transistor. A circuit element is provided for short-circuiting the switching element, and a circuit is provided for writing the information stored in the flip-flop circuit into the nonvolatile memory transistor at the transient of switching off the power.

公开(公告)号：US07336516B2

公开(公告)日：2008-02-26

申请号：US11229191

申请日：2005-09-15

申请人： Hieu Van Tran ,  Hung Q. Nguyen ,  Vishal Sarin ,  Loc B. Hoang ,  Isao Nojima

发明人： Hieu Van Tran ,  Hung Q. Nguyen ,  Vishal Sarin ,  Loc B. Hoang ,  Isao Nojima

IPC分类号： G11C15/00

CPC分类号： G11C16/22 ,  G11C11/5642 ,  G11C15/00 ,  G11C15/04 ,  G11C15/046 ,  G11C16/26 ,  G11C2211/5641

摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

摘要翻译： 统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。 数据或代码可以存储在单独的数组或公共数组中。 在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。 标记位可能表示通信接口或IO驱动程序类型。 感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。 统一存储器中包含XCAM（例如，CAM）阵列。 包括统一内存并发。

公开(公告)号：US06246634B1

公开(公告)日：2001-06-12

申请号：US09562490

申请日：2000-05-01

申请人： Isao Nojima

发明人： Isao Nojima

IPC分类号： G11C800

CPC分类号： G11C16/22 ,  G11C11/418

摘要： An integrated memory circuit has two flash memory arrays and at least one SRAM memory array. The three memory arrays are interconnected by an external address bus and data bus to a main control decoder sequencer which interfaces with the external environment. In addition, the flash and SRAM memory arrays are connected by an internal address and data bus. Through the use of modified software data protection scheme, erase and programming of one flash memory array can occur simultaneously with the reading or writing of data from the SRAM array or the reading of data from the other flash memory array. In addition, data transfer between one flash memory array and the SRAM memory array can occur simultaneously while reading of data occurs from the other flash memory array.

摘要翻译： 集成存储器电路具有两个闪存阵列和至少一个SRAM存储器阵列。 三个存储器阵列通过外部地址总线和数据总线互连到与外部环境接口的主控制解码器定序器。 此外，闪存和SRAM存储器阵列通过内部地址和数据总线连接。 通过使用修改的软件数据保护方案，可以同时从SRAM阵列读取或写入数据或从其他闪存阵列读取数据同时擦除和编程一个闪存阵列。 另外，一个闪速存储器阵列和SRAM存储器阵列之间的数据传输可以同时发生，而数据从另一个闪存阵列发生。

公开(公告)号：US07019998B2

公开(公告)日：2006-03-28

申请号：US10659226

申请日：2003-09-09

申请人： Hieu Van Tran ,  Hung Q. Nguyen ,  Vishal Sarin ,  Loc B. Hoang ,  Isao Nojima

发明人： Hieu Van Tran ,  Hung Q. Nguyen ,  Vishal Sarin ,  Loc B. Hoang ,  Isao Nojima

IPC分类号： G11C15/00

CPC分类号： G11C16/22 ,  G11C11/5642 ,  G11C15/00 ,  G11C15/04 ,  G11C15/046 ,  G11C16/26 ,  G11C2211/5641

摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

摘要翻译： 统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。 数据或代码可以存储在单独的数组或公共数组中。 在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。 标记位可能表示通信接口或IO驱动程序类型。 感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。 统一存储器中包含XCAM（例如，CAM）阵列。 包括统一内存并发。

公开(公告)号：US20050052934A1

公开(公告)日：2005-03-10

申请号：US10659226

申请日：2003-09-09

申请人： Hieu Tran ,  Hung Nguyen ,  Vishal Sarin ,  Loc Hoang ,  Isao Nojima

发明人： Hieu Tran ,  Hung Nguyen ,  Vishal Sarin ,  Loc Hoang ,  Isao Nojima

IPC分类号： G11C11/56 ,  G11C15/04 ,  G11C16/22 ,  G11C16/26 ,  G11C8/00

CPC分类号： G11C16/22 ,  G11C11/5642 ,  G11C15/00 ,  G11C15/04 ,  G11C15/046 ,  G11C16/26 ,  G11C2211/5641

摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

摘要翻译： 统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。 数据或代码可以存储在单独的数组或公共数组中。 在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。 标记位可能表示通信接口或IO驱动程序类型。 感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。 统一存储器中包含XCAM（例如，CAM）阵列。 包括统一内存并发。

公开(公告)号：US5161157A

公开(公告)日：1992-11-03

申请号：US802005

申请日：1991-11-27

申请人： William H. Owen ,  John Caywood ,  Joseph Drori ,  James Jaffe ,  Isao Nojima ,  Jeffrey Sung ,  Ping Wang

发明人： William H. Owen ,  John Caywood ,  Joseph Drori ,  James Jaffe ,  Isao Nojima ,  Jeffrey Sung ,  Ping Wang

IPC分类号： G06F11/00 ,  G11C29/00

CPC分类号： G11C29/789 ,  G06F11/006 ,  G11C29/835 ,  G11C29/838

摘要： A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundancy apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

摘要翻译： 公开了一种用于集成电路半导体存储器阵列的现场可编程冗余装置。 本发明允许用户在集成电路存储器阵列处于现场时用冗余存储器单元替换有缺陷的存储单元。 用户通过集成电路半导体存储器阵列的标准信号路径与标准电压电平与冗余设备进行通信。 冗余设备在存储器阵列的一个或多个地址和数据线上检测预定的代码序列，以进入特殊的冗余重新配置模式。 在重新配置模式中，冗余设备提供关于冗余存储器单元的可用性和功能的信息，并且使得用户能够用所选择的冗余存储器单元来替换有缺陷的存储器单元。 现场可编程冗余设备可以包括非易失性存储器装置，例如EEPROM，用于存储具有冗余存储器单元的主存储器单元的替换。 在重新配置模式中，第二预定代码序列的检测导致重新配置模式被退出。

公开(公告)号：US4980859A

公开(公告)日：1990-12-25

申请号：US335112

申请日：1989-04-07

申请人： Daniel C. Guterman ,  Isao Nojima ,  Ping Wang

发明人： Daniel C. Guterman ,  Isao Nojima ,  Ping Wang

IPC分类号： G11C17/00 ,  G11C14/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C14/00

摘要： A nonvolatile, semiconductor randon access memory cell comprising a static RAM element and a nonvolatile memory element having differential charge storage capabilities is presented. The static RAM and nonvolatile memory elements are interconnected to allow information to be exchanged between two elements, thus allowing the faster static RAM element to serve as the primary memory to the system and allowing the nonvolatile memory element to serve as permanent storage during power-down conditions. In one embodiment, the nonvolatile memory element comprises two electrically erasable PROM devices (EEPROMs). The two EEPROM devices store differential charges corresponding to the complementary outputs of the static RAM element. The nature of the differential charge storage allows lower programming voltages to be used on the EEPROM devices, resulting in increased storage intergrity and increased endurance of the EEPROM devices.

摘要翻译： 提供了一种包括静态RAM元件和具有差分电荷存储能力的非易失性存储元件的非易失性半导体随机存取存储单元。 静态RAM和非易失性存储器元件互连以允许在两个元件之间交换信息，从而允许更快的静态RAM元件用作系统的主要存储器，并允许非易失性存储器元件在断电期间用作永久存储器 条件。 在一个实施例中，非易失性存储元件包括两个电可擦除PROM器件（EEPROM）。 两个EEPROM器件存储对应于静态RAM元件的互补输出的差分电荷。 差分电荷存储器的性质允许在EEPROM器件上使用更低的编程电压，从而增加了EEPROM器件的存储整合性和更高的耐用性。

公开(公告)号：US20080278986A1

公开(公告)日：2008-11-13

申请号：US12176281

申请日：2008-07-18

申请人： Vishal Sarin ,  Hieu Van Tran ,  Isao Nojima

发明人： Vishal Sarin ,  Hieu Van Tran ,  Isao Nojima

IPC分类号： G11C15/04

CPC分类号： G11C14/00 ,  G11C15/046

摘要： A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.

摘要翻译： 差分非易失性内容可寻址存储器阵列具有使用一对非易失性存储元件的差分非易失性内容可寻址存储器单元。 每个非易失性存储元件可以是分离栅极浮栅晶体管或堆叠栅极浮栅晶体管，其具有第一端子，第二端子，其间的沟道以及通道的至少一部分上的浮置栅极以控制 通道中的电子传导，以及控制栅极。 浮置栅极存储晶体管可以处于以下两种状态之一：电流可以在第一端子和第二端子之间流动的第一状态，例如擦除，以及第二状态，诸如编程的，其中基本上没有电流流动 在第一端子和第二端子之间。 一对差分比较数据线连接到该对非易失性浮栅晶体管中的每一个的控制栅极。 匹配线将一对非易失性浮栅晶体管的每一个的第一端连接到第一电压。 最后，每个存储元件的第二端子被连接到与第一电压不同的第二电压。 通过存储单元的电流表示比较数据线的内容与存储元件的内容之间的错误匹配。

公开(公告)号：US07212459B2

公开(公告)日：2007-05-01

申请号：US11126495

申请日：2005-05-10

申请人： Hieu Van Tran ,  Hung Q. Nguyen ,  Vishal Sarin ,  Loc B. Hoang ,  Isao Nojima

发明人： Hieu Van Tran ,  Hung Q. Nguyen ,  Vishal Sarin ,  Loc B. Hoang ,  Isao Nojima

IPC分类号： G11C7/02

CPC分类号： G11C16/22 ,  G11C11/5642 ,  G11C15/00 ,  G11C15/04 ,  G11C15/046 ,  G11C16/26 ,  G11C2211/5641

摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

摘要翻译： 统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。 数据或代码可以存储在单独的数组或公共数组中。 在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。 标记位可能表示通信接口或IO驱动程序类型。 感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。 统一存储器中包含XCAM（例如，CAM）阵列。 包括统一内存并发。

公开(公告)号：US06809425B1

公开(公告)日：2004-10-26

申请号：US10641610

申请日：2003-08-15

申请人： Bomy Chen ,  Isao Nojima ,  Hung Q. Nguyen

发明人： Bomy Chen ,  Isao Nojima ,  Hung Q. Nguyen

IPC分类号： H01L27088

CPC分类号： H03K19/17748 ,  H01L27/101 ,  H03K19/1778 ,  Y10S257/901

摘要： A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor, which is in a well, with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a first region and a second region, with a channel therebetween. The cell has a floating gate positioned over a first portion of the channel, which is adjacent to the first region and a control gate positioned over a second portion of the channel, which is adjacent to the second region. The second region is connected to the gate of the MOS transistor. The cell is programmed by injecting electrons from the channel onto the floating gate by hot electron injection mechanism. The cell is erased by Fowler-Nordheim tunneling of the electrons from the floating gate to the control gate. As a result, no high voltage is ever applied to the second region during program or erase. In addition, a MOS FET transistor has a terminal connected to the well, and another end to a voltage source, with the gate connected to the non-volatile memory cell. The switch also has a circuit element connecting the gate of the MOS transistor to a voltage source. The threshold voltage of the well can be dynamically changed by turning on/off the MOS FET transistor.

摘要翻译： 用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管位于阱中，MOS晶体管的端子连接到信号源和电路。 非易失性存储单元是具有第一区域和第二区域的分离栅极类型，其间具有沟道。 电池具有位于通道第一部分上方的浮动栅极，该第一部分与第一区域相邻，并且控制栅极位于与第二区域相邻的通道的第二部分上方。 第二区域连接到MOS晶体管的栅极。 通过热电子注入机制将电子从通道注入到浮动栅上来编程电池。 Fowler-Nordheim将电池从浮动栅极隧穿到控制栅极，从而消除电池。 因此，在编程或擦除期间，不会对第二区域施加高电压。 此外，MOS FET晶体管具有连接到阱的端子，另一端连接到电压源，栅极连接到非易失性存储单元。 该开关还具有将MOS晶体管的栅极连接到电压源的电路元件。 通过接通/关断MOS FET晶体管可以动态地改变阱的阈值电压。