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34 条记录 (耗时 0.034 秒)

    Dynamic memory device with an RC circuit for inhibiting the effects of alpha particle radiation
    1.
    发明授权
    Dynamic memory device with an RC circuit for inhibiting the effects of alpha particle radiation 失效
    具有用于抑制α粒子辐射影响的RC电路的动态存储器件

    公开(公告)号：US4641165A

    公开(公告)日：1987-02-03

    申请号：US475554

    申请日：1983-03-15

    申请人： Tetsuya Iizuka ,  Syuso Fujii ,  Yukimasa Uchida

    发明人： Tetsuya Iizuka ,  Syuso Fujii ,  Yukimasa Uchida

    IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L27/14

    CPC分类号： G11C11/404 ,  H01L27/10805

    摘要： The dynamic memory device of the present invention is formed on an integrated semiconductor substrate subjected to alpha radiation and comprises a switching transistor having a switching terminal, an input-output terminal and a memory terminal; a bit line couple to said input-output terminal for supplying a charge to said transistor; a word line coupled to said switching terminal for controlling the switching of said transistor; and, an R-C circuit coupled to the memory terminal and comprising a charge storage capacitor for storing the charge supplied from said bit line and for substantially preventing loss of the stored charge due to particle radiation.

    摘要翻译： 本发明的动态存储器件形成在经受α辐射的集成半导体衬底上，并且包括具有开关端子，输入输出端子和存储器端子的开关晶体管; 位线耦合到所述输入输出端子，用于向所述晶体管提供电荷; 耦合到所述开关端子用于控制所述晶体管的开关的字线; 以及R-C电路，其耦合到存储器端子并且包括用于存储从所述位线提供的电荷的电荷存储电容器，并且用于基本上防止由于粒子辐射引起的存储电荷的损失。

    TTL to CMOS buffer circuit
    3.
    发明授权
    TTL to CMOS buffer circuit 失效
    TTL到CMOS缓冲电路

    公开(公告)号：US5019729A

    公开(公告)日：1991-05-28

    申请号：US382493

    申请日：1989-07-21

    申请人： Tohru Kimura ,  Syuso Fujii ,  Takashi Ohsawa

    发明人： Tohru Kimura ,  Syuso Fujii ,  Takashi Ohsawa

    IPC分类号： G11C11/409 ,  H03K19/0185

    CPC分类号： H03K19/018528 ,  H03K19/01855

    摘要： A buffer circuit includes first and second differential amplification type buffer circuits. The input nodes of the first and second differential amplification type buffer circuits are connected together and the output nodes of the first and second differential amplification type buffer circuits are also connected to each other. The first differential amplification type buffer circuit is constituted by a pair of driving P-channel MOS transistors and N-channel MOS transistors acting as loads of the P-channel MOS transistors and connected to constitute a current mirror circuit. The second differential amplification type buffer circuit is constituted by P-channel MOS transistors acting as loads and connected to constitute a current mirror circuit and a pair of driving N-channel MOS transistors.

    摘要翻译： 缓冲电路包括第一和第二差分放大型缓冲电路。 第一和第二差分放大型缓冲电路的输入节点连接在一起，并且第一和第二差分放大型缓冲电路的输出节点也彼此连接。 第一差分放大型缓冲电路由作为P沟道MOS晶体管的负载的一对驱动P沟道MOS晶体管和N沟道MOS晶体管构成，并连接构成电流镜电路。 第二差分放大型缓冲电路由作为负载的P沟道MOS晶体管构成，并连接构成电流镜电路和一对驱动N沟道MOS晶体管。

    Input protection circuit for semiconductor integrated circuit device
    4.
    发明授权
    Input protection circuit for semiconductor integrated circuit device 失效
    半导体集成电路器件的输入保护电路

    公开(公告)号：US4994874A

    公开(公告)日：1991-02-19

    申请号：US425950

    申请日：1989-10-24

    申请人： Mitsuru Shimizu ,  Yoshio Okada ,  Syuso Fujii ,  Shozo Saito

    发明人： Mitsuru Shimizu ,  Yoshio Okada ,  Syuso Fujii ,  Shozo Saito

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02

    CPC分类号： H01L27/0259

    摘要： First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad. The first impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the first and third impurity regions constitute a first bipolar transistor for input protection and the second impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the second and third impurity regions constitute a second bipolar transistor for input protection. The resistor and the first and second bipolar transistors constitute an input protection circuit.

    摘要翻译： 在N型半导体衬底中形成的P型半导体衬底或P阱区域的表面区域中，第一至第三N +型杂质区彼此分开地预定距离地形成。 第一杂质区域连接到电源，第二杂质区域连接到接地端子。 形成在第一和第二杂质区域之间的第三杂质区域连接到另一端连接到信号输入焊盘的输入保护电阻器的一端。 位于第一和第三杂质区域之间的第一杂质区域，第三杂质区域和P型半导体衬底或P阱区域的部分构成用于输入保护的第一双极晶体管，第二杂质区域，第三杂质区域 位于第二和第三杂质区之间的P型半导体衬底或P阱区的部分构成用于输入保护的第二双极晶体管。 电阻器和第一和第二双极晶体管构成输入保护电路。

    Semiconductor memory having barrier transistors connected between sense and restore circuits
    6.
    发明授权
    Semiconductor memory having barrier transistors connected between sense and restore circuits 失效
    半导体存储器具有连接在感测和恢复电路之间的阻挡晶体管

    公开(公告)号：US4931992A

    公开(公告)日：1990-06-05

    申请号：US310020

    申请日：1989-02-09

    申请人： Masaki Ogihara ,  Yoshio Okada ,  Syuso Fujii

    发明人： Masaki Ogihara ,  Yoshio Okada ,  Syuso Fujii

    IPC分类号： G11C11/4094

    CPC分类号： G11C11/4094

    摘要： A semiconductor memory comprises a memory cell for storing data, a bit line pair for transfering the data, a sense amplifier for amplifying the data from the bit line pair, a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory, and a pair of constant voltage barrier transistors connected between the restore circuit and the sense amplifier for increasing the speed of sensing.

    摘要翻译： 半导体存储器包括用于存储数据的存储单元，用于传送数据的位线对，用于放大来自位线对的数据的读出放大器，直接连接到位线对的恢复电路，用于恢复半导体中的数据 存储器和连接在恢复电路和读出放大器之间的一对恒定电压势垒晶体管，用于增加感测速度。

    Semiconductor memory apparatus with configured word lines to reduce noise
    7.
    发明授权
    Semiconductor memory apparatus with configured word lines to reduce noise 失效
    具有配置字线以减少噪声的半导体存储器件

    公开(公告)号：US5420816A

    公开(公告)日：1995-05-30

    申请号：US299086

    申请日：1994-08-31

    申请人： Masaki Ogihara ,  Syuso Fujii

    发明人： Masaki Ogihara ,  Syuso Fujii

    IPC分类号： G11C11/407 ,  G11C8/14 ,  G11C11/401 ,  G11C5/06

    CPC分类号： G11C8/14

    摘要： According to this invention, a semiconductor apparatus includes a word line group consisting of four word lines, a bit line pair group, word line drive circuits, arrangement patterns of which are alternately inverted, for outputting boosted word line signals to the word line group, and memory contact portions provided to the bit line pair group in a 1/4-pitch system, wherein output terminals of the word line drive circuit having an inverted arrangement pattern are connected to memory cells so as to be aligned in the same order as in output terminals of the word line drive circuit having a non-inverted arrangement pattern.

    摘要翻译： 根据本发明，半导体装置包括由四个字线组成的字线组，位线对组，字线驱动电路，交替反转的排列图案，用于将升压的字线信号输出到字线组， 以及以1/4间距系统提供给位线对组的存储器接触部分，其中具有反向排列图案的字线驱动电路的输出端子连接到存储器单元，以便按照与 字线驱动电路的输出端子具有非反相布置图案。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5016224A

    公开(公告)日：1991-05-14

    申请号：US404421

    申请日：1989-09-08

    申请人： Hiroto Tanaka ,  Syuso Fujii

    发明人： Hiroto Tanaka ,  Syuso Fujii

    IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4097

    CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4097

    摘要： First sense amplifiers formed of N-channel transistors are disposed between first and second memory cell blocks. Second sense amplifiers formed of P-channel transistors are disposed between second and third memory cell blocks. Switching transistors are disposed between the sense amplifiers and the memory cell blocks in order to select a particular memory cell block in response to signals applied to the gates thereof.

    摘要翻译： 由N沟道晶体管形成的第一读出放大器设置在第一和第二存储单元块之间。 由P沟道晶体管形成的第二感测放大器设置在第二和第三存储单元块之间。 开关晶体管设置在感测放大器和存储器单元块之间，以便响应于施加到其栅极的信号来选择特定存储器单元块。