公开(公告)号：US20230009881A1

公开(公告)日：2023-01-12

申请号：US17371459

申请日：2021-07-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Eric J. Chapman ,  Alan D. Smith ,  Edward Chang

IPC: G06F1/28

Abstract: A multi-die processor semiconductor package includes a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies. In some embodiments, the semiconductor package also includes a second base IC die including a second plurality of compute dies 3D stacked on top of the second base IC die and an interconnect communicably coupling the first base IC die to the second base IC die.

公开(公告)号：US11233510B2

公开(公告)日：2022-01-25

申请号：US15965186

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Edward Chang

IPC: G11C7/06 ,  H03K19/00 ,  G11C11/412 ,  G11C11/419 ,  G06F3/06 ,  G11C11/418

Abstract: Systems, apparatuses, and methods for efficiently performing operations system are disclosed. A computing system uses a memory for storing data, and one or more processing units. The memory includes multiple rows for storing the data with each intersection of a row and a column being a memory bit cell. The memory processes operations. For particular operations, the two or more operands are accessed simultaneously for generating a result without being read out and stored. Two indications are generated specifying at least a first row and a second row targeted by the operation. The memory generates a result by performing the operation for each of the one or more cells in the first row a stored value with a respective stored value in the one or more cells in the second row.

公开(公告)号：US20190334524A1

公开(公告)日：2019-10-31

申请号：US15965186

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Edward Chang

IPC: H03K19/00 ,  G11C11/412 ,  G11C11/419 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for efficiently performing operations system are disclosed. A computing system uses a memory for storing data, and one or more processing units. The memory includes multiple rows for storing the data with each intersection of a row and a column being a memory bit cell. The memory processes operations. For particular operations, the two or more operands are accessed simultaneously for generating a result without being read out and stored. Two indications are generated specifying at least a first row and a second row targeted by the operation. The memory generates a result by performing the operation for each of the one or more cells in the first row a stored value with a respective stored value in the one or more cells in the second row.

公开(公告)号：US12107076B2

公开(公告)日：2024-10-01

申请号：US17564137

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Wonjun Jung ,  Jasmeet Singh Narang ,  Tyrone Huang ,  Christopher Klement ,  Alan D. Smith ,  Edward Chang ,  John Wuu

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L25/0652 ,  H01L2225/06544

Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.

公开(公告)号：US11960339B2

公开(公告)日：2024-04-16

申请号：US17371459

申请日：2021-07-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Eric J. Chapman ,  Alan D. Smith ,  Edward Chang

IPC: G06F1/28 ,  H01L25/18

CPC classification number: G06F1/28 ,  H01L25/18

Abstract: A multi-die processor semiconductor package includes a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies. In some embodiments, the semiconductor package also includes a second base IC die including a second plurality of compute dies 3D stacked on top of the second base IC die and an interconnect communicably coupling the first base IC die to the second base IC die.