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公开(公告)号：US20230097344A1
公开(公告)日：2023-03-30
申请号：US17487247
申请日：2021-09-28
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Joseph L. Greathouse , Alan D. Smith , Francisco L. Duran , Felix Kuehling , Anthony Asaro
Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
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公开(公告)号：US20240220409A1
公开(公告)日：2024-07-04
申请号：US18090249
申请日：2022-12-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Vydhyanathan Kalyanasundharam , Alan D. Smith , Chintan S. Patel , William L. Walker
IPC: G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/1024
Abstract: The disclosed computer-implemented method includes partitioning a cache structure into a plurality of cache partitions designated by a plurality of cache types, forwarding a memory request to a cache partition corresponding to a target cache type of the memory request, and performing, using the cache partition, the memory request. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US11995351B2
公开(公告)日：2024-05-28
申请号：US17515976
申请日：2021-11-01
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Joseph L Greathouse , Sean Keely , Alan D. Smith , Anthony Asaro , Ling-Ling Wang , Milind N Nemlekar , Hari Thangirala , Felix Kuehling
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0679 , G06F13/28
Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.
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公开(公告)号：US20230384947A1
公开(公告)日：2023-11-30
申请号：US18208639
申请日：2023-06-12
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Joseph L. Greathouse , Alan D. Smith , Francisco L. Duran , Felix Kuehling , Anthony Asaro
CPC classification number: G06F3/0619 , G06F3/064 , G06F12/0607 , G06F3/0659 , G06F3/0673 , G06F3/0644
Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
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公开(公告)号：US11830817B2
公开(公告)日：2023-11-28
申请号：US17085215
申请日：2020-10-30
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Rahul Agarwal , Raja Swaminathan , Michael S. Alfano , Gabriel H. Loh , Alan D. Smith , Gabriel Wong , Michael Mantor
IPC: H01L23/538 , H01L25/065 , H01L21/50 , H01L27/06
CPC classification number: H01L23/5384 , H01L21/50 , H01L23/5381 , H01L23/5385 , H01L25/0657 , H01L27/0688
Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.
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Patent Agency Ranking
公开(公告)号：US20230009881A1
公开(公告)日：2023-01-12
申请号：US17371459
申请日：2021-07-09
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Eric J. Chapman , Alan D. Smith , Edward Chang
IPC: G06F1/28
Abstract: A multi-die processor semiconductor package includes a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies. In some embodiments, the semiconductor package also includes a second base IC die including a second plurality of compute dies 3D stacked on top of the second base IC die and an interconnect communicably coupling the first base IC die to the second base IC die.
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公开(公告)号：US12107076B2
公开(公告)日：2024-10-01
申请号：US17564137
申请日：2021-12-28
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Wonjun Jung , Jasmeet Singh Narang , Tyrone Huang , Christopher Klement , Alan D. Smith , Edward Chang , John Wuu
IPC: H01L25/065 , H01L23/48
CPC classification number: H01L25/0657 , H01L23/481 , H01L25/0652 , H01L2225/06544
Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.
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公开(公告)号：US20240202047A1
公开(公告)日：2024-06-20
申请号：US18082882
申请日：2022-12-16
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Joseph L. Greathouse , Alan D. Smith , Anthony Asaro , Kostantinos Danny Christidis , Alexander Fuad Ashkar , Milind N. Nemlekar
CPC classification number: G06F15/7825 , G06F9/522
Abstract: The disclosed computer-implemented method can include reaching, by a chiplet involved in carrying out an operation for a process, a synchronization barrier. The method can additionally include receiving, by the chiplet, dedicated control messages pushed to the chiplet by other chiplets involved in carrying out the operation for the process, wherein the dedicated control messages are pushed over a control network by the other chiplets. The method can also include advancing, by the chiplet, the synchronization barrier in response to receipt of the dedicated control messages. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US11960339B2
公开(公告)日：2024-04-16
申请号：US17371459
申请日：2021-07-09
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Eric J. Chapman , Alan D. Smith , Edward Chang
Abstract: A multi-die processor semiconductor package includes a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies. In some embodiments, the semiconductor package also includes a second base IC die including a second plurality of compute dies 3D stacked on top of the second base IC die and an interconnect communicably coupling the first base IC die to the second base IC die.
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公开(公告)号：US11687251B2
公开(公告)日：2023-06-27
申请号：US17487247
申请日：2021-09-28
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Joseph L. Greathouse , Alan D. Smith , Francisco L. Duran , Felix Kuehling , Anthony Asaro
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0673 , G06F12/0607
Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
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