公开(公告)号：US20200027491A1

公开(公告)日：2020-01-23

申请号：US16470969

申请日：2017-12-18

Applicant: Agency for Science, Technology and Research

Inventor： Xuanyao Fong ,  Anh Tuan Do ,  Xin Liu

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: Various embodiments may provide a memory cell. The memory cell may include a magnetic tunneling junction memory including a first end and a second end. The memory cell may include a first transistor including a control electrode, a first controlled electrode and a second controlled electrode. The memory cell may also include a second transistor including a control electrode, a first controlled electrode and a second controlled electrode. The memory cell may additionally include a diode having a first end and a second end. In various embodiments, the memory cell may include a further magnetic tunneling junction memory, and a third transistor.

公开(公告)号：US12255997B2

公开(公告)日：2025-03-18

申请号：US17799898

申请日：2020-02-26

Applicant: Agency for Science, Technology and Research

Inventor： Ming Ming Wong ,  Anh Tuan Do ,  Kevin Tshun Chuan Chai

IPC: G06F21/42 ,  H04L9/00 ,  H04L9/08 ,  H04L9/12 ,  G06F12/14 ,  G06F21/32

Abstract: There is provided a method of communication between functional blocks in a system-on-chip. The method includes: exchanging a respective public key between a first functional block and a second functional block in the system-on-chip (SoC) for a communication therebetween, the first functional block being a transmitter of the communication and the second function block being a receiver of the communication; generating, at the first functional block, a first code based on the public key of the second functional block; generating, at the second functional block, a second code based on the public key of the first functional block; obfuscating, at the first functional block, an address associated with the communication based on the first code to produce an obfuscated address; transmitting, at the first functional block, the obfuscated address to the second functional block via an interconnect communication infrastructure in the system-on-chip; receiving, at the second functional block, the obfuscated address from the first functional block via the interconnect communication infrastructure; and deobfuscating, at the second functional block, the obfuscated address received based on the second code to produce a deobfuscated address associated with the communication. There is also provided a corresponding system-on-chip.

公开(公告)号：US11978506B2

公开(公告)日：2024-05-07

申请号：US18039414

申请日：2020-12-10

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Di Zhu ,  Kevin Tshun Chuan Chai ,  Aarthy Mani ,  Anh Tuan Do

IPC: G11C11/418 ,  G02F1/133 ,  G02F1/1343 ,  G02F1/1368 ,  G09G3/36

CPC classification number: G11C11/418 ,  G02F1/13306 ,  G02F1/13439 ,  G02F1/1368 ,  G09G3/3648 ,  G02F2203/12 ,  G09G2300/0857 ,  G09G2310/08

Abstract: This document describes a spatial light modulator that comprises a pixel array having a plurality of pixels whereby each pixel in this array is communicatively coupled to a digital pixel circuit which are in turn all coupled to a bit-plane control circuit. The bit-plane control circuit is configured to generate, using a Pulse Code Modulation (PCM) algorithm, bit-plane signals that are used to control the sample and hold functions performed by each of the digital pixel circuits so that the pixel array may carry out its scanning function accurately and in a power efficient manner.

公开(公告)号：US20220222513A1

公开(公告)日：2022-07-14

申请号：US17638748

申请日：2019-09-03

Applicant: Agency for Science, Technology and Research

Inventor： Vishnu Paramasivam ,  Anh Tuan Do ,  Eng Kiat Koh ,  Junran Pu ,  Fei Li ,  Aarthy Mani

IPC: G06N3/063 ,  G06N3/04

Abstract: There is provided a neural network processor system including: a plurality of neural processing units, including a first neural processing unit and a second neural processing unit, whereby each neural processing unit comprises an array of neural processing core blocks, each neural processing core block comprising a neural processing core; and at least one central processing unit communicatively coupled to the plurality of neural processing units and configured to coordinate the plurality of neural processing units for performing neural network computations. In particular, the first and second neural processing units have a different structural configuration to each other. There is also provided a corresponding method of operating and a corresponding method of forming the neural network processor system.

公开(公告)号：US11023207B1

公开(公告)日：2021-06-01

申请号：US16074210

申请日：2017-02-24

Applicant: Agency for Science, Technology and Research

Inventor： Anh Tuan Do

IPC: G06F7/58 ,  H03K19/21

Abstract: Embodiments provide a true random number generator. The true random number generator may include a first ring oscillator having a first frequency, a second ring oscillator having a second frequency, a third ring oscillator having a third frequency, and a capacitor connected between the second ring oscillator and the third ring oscillator to provide a capacitive coupling therebetween. The second frequency is lower than the first frequency, and the third frequency is lower than the second frequency. The true random number generator may further include a D-type flip-flop having a data input connected to an output of the first ring oscillator and having a clock input connected to an output of the third ring oscillator, wherein the D-type flip-flop is configured to generate an output signal representing a sequence of random numbers.

公开(公告)号：US20210141608A1

公开(公告)日：2021-05-13

申请号：US16074210

申请日：2017-02-24

Applicant: Agency for Science, Technology and Research

Inventor： Anh Tuan Do

IPC: G06F7/58 ,  H03K19/21

Abstract: Embodiments provide a true random number generator. The true random number generator may include a first ring oscillator having a first frequency, a second ring oscillator having a second frequency, a third ring oscillator having a third frequency, and a capacitor connected between the second ring oscillator and the third ring oscillator to provide a capacitive coupling therebetween. The second frequency is lower than the first frequency, and the third frequency is lower than the second frequency. The true random number generator may further include a D-type flip-flop having a data input connected to an output of the first ring oscillator and having a clock input connected to an output of the third ring oscillator, wherein the D-type flip-flop is configured to generate an output signal representing a sequence of random numbers.