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    NEURAL NETWORK PROCESSOR SYSTEM AND METHODS OF OPERATING AND FORMING THEREOF
    2.
    发明申请
    NEURAL NETWORK PROCESSOR SYSTEM AND METHODS OF OPERATING AND FORMING THEREOF 有权

    公开(公告)号：US20220222513A1

    公开(公告)日：2022-07-14

    申请号：US17638748

    申请日：2019-09-03

    Applicant: Agency for Science, Technology and Research

    Inventor： Vishnu Paramasivam ,  Anh Tuan Do ,  Eng Kiat Koh ,  Junran Pu ,  Fei Li ,  Aarthy Mani

    IPC: G06N3/063 ,  G06N3/04

    Abstract: There is provided a neural network processor system including: a plurality of neural processing units, including a first neural processing unit and a second neural processing unit, whereby each neural processing unit comprises an array of neural processing core blocks, each neural processing core block comprising a neural processing core; and at least one central processing unit communicatively coupled to the plurality of neural processing units and configured to coordinate the plurality of neural processing units for performing neural network computations. In particular, the first and second neural processing units have a different structural configuration to each other. There is also provided a corresponding method of operating and a corresponding method of forming the neural network processor system.

    Methods and circuit arrangements for determining resistances
    3.
    发明授权
    Methods and circuit arrangements for determining resistances 有权

    公开(公告)号：US09697894B2

    公开(公告)日：2017-07-04

    申请号：US14225367

    申请日：2014-03-25

    Applicant: Agency for Science, Technology and Research

    Inventor： Fei Li ,  Kit Ho Melvin Chow

    IPC: G01R27/02 ,  G11C13/00 ,  G11C11/16 ,  G11C29/24 ,  G11C29/50

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0002 ,  G11C29/24 ,  G11C29/50008 ,  G11C2013/0054

    Abstract: A method may include applying a first current through the memory element and a first selection component. The memory element and the first selection component may be located along a memory line. The method may also include measuring a first potential difference across the memory line. The method may further include applying a second current through a second selection component, wherein the second selection component is located along a dummy line, and measuring a second potential difference across the dummy line. The method may additionally include determining the resistance of the memory element based on the first potential difference and the second potential difference. The first selection component may be activated and the second selection component may be deactivated to apply the first current. The first selection component may be deactivated and the second selection component may be activated to apply the second current.

    Circuit arrangement and method of forming the same
    4.
    发明授权
    Circuit arrangement and method of forming the same 有权
    电路布置及其形成方法

    公开(公告)号：US09030865B2

    公开(公告)日：2015-05-12

    申请号：US14057222

    申请日：2013-10-18

    Applicant: Agency for Science, Technology and Research

    Inventor： Kit Ho Melvin Chow ,  Fei Li

    IPC: G11C5/06 ,  G11C5/02 ,  G11C5/08 ,  G11C8/00 ,  G11C7/00 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00

    CPC classification number: G11C11/1673 ,  G11C5/02 ,  G11C5/06 ,  G11C8/00 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5607 ,  G11C13/0069

    Abstract: In various embodiments, a circuit arrangement may be provided including a data cell. The circuit arrangement may further include a first transistor and a second transistor. The first controlled electrode of the first transistor and the first controlled electrode of the second transistor may be coupled to the first electrode of the data cell. The second controlled electrode of the first transistor may be configured to electrically connect to a first reference voltage such that the first electrode of the data cell is electrically connected to the first reference voltage when the first transistor is activated. The second controlled electrode of the second transistor may be configured to electrically connect to a second reference voltage, such that the first electrode of the data cell is electrically connected to the second reference voltage when the second transistor is activated.

    Abstract translation: 在各种实施例中，可以提供包括数据单元的电路装置。 电路装置还可以包括第一晶体管和第二晶体管。 第一晶体管的第一受控电极和第二晶体管的第一受控电极可以耦合到数据单元的第一电极。 第一晶体管的第二受控电极可以被配置为电连接到第一参考电压，使得当第一晶体管被激活时，数据单元的第一电极电连接到第一参考电压。 第二晶体管的第二受控电极可以被配置为电连接到第二参考电压，使得当第二晶体管被激活时，数据单元的第一电极电连接到第二参考电压。

    Memory cell, memory array, method of forming and operating memory cell
    6.
    发明授权
    Memory cell, memory array, method of forming and operating memory cell 有权

    公开(公告)号：US10923648B2

    公开(公告)日：2021-02-16

    申请号：US16478195

    申请日：2018-01-17

    Applicant: Agency for Science, Technology and Research

    Inventor： Karim Ali Abdeltawwab Ahmed ,  Sunny Yan Hwee Lua ,  Fei Li

    IPC: G11C11/00 ,  H01L43/02 ,  G11C11/16 ,  G11C11/56 ,  H01F10/32 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

    Abstract: Various embodiments may relate to a memory cell. The memory cell may include a first cell electrode, a first insulator layer and a first magnetic free layer between the first cell electrode and the first insulator layer. The memory cell may also include a second cell electrode, a second insulator layer, and a second magnetic free layer between the second cell electrode and the second insulator layer. A magnetic pinned layer may be between the first insulator layer and the second insulator layer. A direction of magnetization of the first magnetic free layer may be changeable in response to a current flowing between a first end and a second end of the first cell electrode. A direction of magnetization of the second magnetic free layer may be changeable in response to a current flowing between a first end and a second end of the second cell electrode.

    MEMORY CELL, MEMORY ARRAY, METHOD OF FORMING AND OPERATING MEMORY CELL
    7.
    发明申请
    MEMORY CELL, MEMORY ARRAY, METHOD OF FORMING AND OPERATING MEMORY CELL 审中-公开

    公开(公告)号：US20190334080A1

    公开(公告)日：2019-10-31

    申请号：US16478195

    申请日：2018-01-17

    Applicant: Agency for Science, Technology and Research

    Inventor： Karim Ali Abdeltawwab Ahmed ,  Sunny Yan Hwee Lua ,  Fei Li

    IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  G11C11/56 ,  H01L27/22 ,  H01F10/32

    Abstract: Various embodiments may relate to a memory cell. The memory cell may include a first cell electrode, a first insulator layer and a first magnetic free layer between the first cell electrode and the first insulator layer. The memory cell may also include a second cell electrode, a second insulator layer, and a second magnetic free layer between the second cell electrode and the second insulator layer. A magnetic pinned layer may be between the first insulator layer and the second insulator layer. A direction of magnetization of the first magnetic free layer may be changeable in response to a current flowing between a first end and a second end of the first cell electrode. A direction of magnetization of the second magnetic free layer may be changeable in response to a current flowing between a first end and a second end of the second cell electrode.

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