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公开(公告)号：US20160179373A1
公开(公告)日：2016-06-23
申请号：US14574527
申请日：2014-12-18
Applicant: APPLE INC.
Inventor： Liran Erez , Guy Ben-Yehuda , Avraham (Poza) Meir , Ori Isachar
IPC: G06F3/06
CPC classification number: G11C11/5628 , G11C7/1045 , G11C7/1063
Abstract: An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.
Abstract translation: 一种装置包括寄存器存储器和电路。 寄存器存储器被配置为保持为给定类型的存储器访问命令的性能测量指定的最小值，其实际性能测量在存储器设备之间变化。 电路被配置为接收给定类型的存储器访问命令，以在一个或多个存储器设备中执行接收的存储器访问命令，并且在达到存储在寄存器存储器中的最小值之前确认存储器访问命令。
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Patent Agency Ranking
公开(公告)号：US09858990B2
公开(公告)日：2018-01-02
申请号：US14574527
申请日：2014-12-18
Applicant: APPLE INC.
Inventor： Liran Erez , Guy Ben-Yehuda , Avraham (Poza) Meir , Ori Isachar
CPC classification number: G11C11/5628 , G11C7/1045 , G11C7/1063
Abstract: An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.
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公开(公告)号：US10762967B2
公开(公告)日：2020-09-01
申请号：US16202130
申请日：2018-11-28
Applicant: Apple Inc.
Inventor： Assaf Shappir , Barak Baum , Itay Sagron , Roman Guy , Guy Ben-Yehuda , Stas Mouler
Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.
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公开(公告)号：US20200005874A1
公开(公告)日：2020-01-02
申请号：US16202130
申请日：2018-11-28
Applicant: Apple Inc.
Inventor： Assaf Shappir , Barak Baum , Itay Sagron , Roman Guy , Guy Ben-Yehuda , Stas Mouler
Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.
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公开(公告)号：US09996417B2
公开(公告)日：2018-06-12
申请号：US15096303
申请日：2016-04-12
Applicant: Apple Inc.
Inventor： Assaf Shappir , Etai Zaltsman , Guy Ben-Yehuda
CPC classification number: G06F11/1072 , G06F11/108 , G11C29/52
Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.
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公开(公告)号：US20170293527A1
公开(公告)日：2017-10-12
申请号：US15096303
申请日：2016-04-12
Applicant: Apple Inc.
Inventor： Assaf Shappir , Etai Zaltsman , Guy Ben-Yehuda
CPC classification number: G06F11/1072 , G06F11/108 , G11C29/52
Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.
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