公开(公告)号：US09741410B2

公开(公告)日：2017-08-22

申请号：US14857527

申请日：2015-09-17

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

IPC: G11C7/00 ,  G11C8/12 ,  G11C5/14 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/419 ,  G11C8/18

CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

公开(公告)号：US09142266B2

公开(公告)日：2015-09-22

申请号：US14083619

申请日：2013-11-19

Applicant: ARM LIMITED

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C7/22 ,  G11C5/14

CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。

公开(公告)号：US20150138901A1

公开(公告)日：2015-05-21

申请号：US14083619

申请日：2013-11-19

Applicant: Arm Limited

Inventor： Andy Wangkun CHEN ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

IPC: G11C7/12 ,  G11C8/12

CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。

公开(公告)号：US20170194046A1

公开(公告)日：2017-07-06

申请号：US14986215

申请日：2015-12-31

Applicant: ARM Limited

Inventor： Gus Yeung, JR. ,  Fakhruddin Ali Bohra ,  George Lattimore

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C8/16 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/2209

Abstract: Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.

公开(公告)号：US09374072B2

公开(公告)日：2016-06-21

申请号：US14268336

申请日：2014-05-02

Applicant: ARM Limited

Inventor： Betina Hold ,  Brian Cline ,  George Lattimore

IPC: H03K5/133 ,  H03K5/13

CPC classification number: H03K5/133

Abstract: An integrated circuit 2 includes a transistor 26 which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract translation: 集成电路2包括晶体管26，其具有在该晶体管的正常操作期间产生正常切换速度，其在正常范围内施加电信号。 如果希望改变晶体管的操作速度，则速度调节电路12将具有超出正常特性范围的调谐特性的调谐电信号施加到相关的晶体管。 调谐电信号引起该晶体管的至少一个物理特性的变化，使得当其恢复其修改的正常操作时，该晶体管的开关速度将改变。 调谐电信号可以是在施加到晶体管的栅极的正常的电压范围之外的电压（或电流），以便引起该晶体管的阈值的永久增加，并因此降低其转换速度。 也可以控制晶体管的温度以引起性能/速度的永久性变化。

公开(公告)号：US20160005448A1

公开(公告)日：2016-01-07

申请号：US14857527

申请日：2015-09-17

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

IPC: G11C8/12 ,  G11C8/18 ,  G11C7/22

CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。