METHOD AND APPARATUS FOR MANAGING MEMORY
    1.
    发明公开

    公开(公告)号:US20240201876A1

    公开(公告)日:2024-06-20

    申请号:US18083306

    申请日:2022-12-16

    CPC classification number: G06F3/0625 G06F3/0644 G06F3/0673

    Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

    COST-SAVING SCHEME FOR SCAN TESTING OF 3D STACK DIE

    公开(公告)号:US20240019493A1

    公开(公告)日:2024-01-18

    申请号:US17866342

    申请日:2022-07-15

    CPC classification number: G01R31/318583 G01R31/318572 G01R31/2834

    Abstract: A system and method for efficiently routing scan data between two dies used in three-dimensional packaging are described. In various implementations, a computing system includes at least a first semiconductor die (or first die) and a second die connected to one another within a three-dimensional (3D) package. The first die and the second die have multiple non-scan input/output (I/O) data channels between them for data transfer. The non-scan I/O data channels are partitioned into groups. The first die receives a given scan input data bit for testing a device under test (DUT) on the second die. The first die selects a first group of non-scan I/O data channels, and sends, to the second die, a copy of the given scan input data bit on each non-scan I/O data channel of the first group. The second die uses a voter circuit to determine the value of the given scan input data bit.

    Systems and methods for enabling debugging

    公开(公告)号:US12181955B1

    公开(公告)日:2024-12-31

    申请号:US18087894

    申请日:2022-12-23

    Abstract: A computer-implemented method for enabling debugging can include receiving, at a peripheral device connected through an expansion socket to a base CPU platform, a scan dump instruction from a network computing device connected to the base CPU platform across a network connection and executing, by a System-on-Chip at the peripheral device in response to the scan dump instruction, a debugging procedure. The debugging procedure can include capturing a snapshot of memory of the peripheral device and transmitting the snapshot to the network computing device through memory addresses that have been assigned to memory-mapped input/output. Various other methods, systems, and computer-readable media are also disclosed.

    Cost-saving scheme for scan testing of 3D stack die

    公开(公告)号:US12099091B2

    公开(公告)日:2024-09-24

    申请号:US17866342

    申请日:2022-07-15

    Abstract: A system and method for efficiently routing scan data between two dies used in three-dimensional packaging are described. In various implementations, a computing system includes at least a first semiconductor die (or first die) and a second die connected to one another within a three-dimensional (3D) package. The first die and the second die have multiple non-scan input/output (I/O) data channels between them for data transfer. The non-scan I/O data channels are partitioned into groups. The first die receives a given scan input data bit for testing a device under test (DUT) on the second die. The first die selects a first group of non-scan I/O data channels, and sends, to the second die, a copy of the given scan input data bit on each non-scan I/O data channel of the first group. The second die uses a voter circuit to determine the value of the given scan input data bit.

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