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    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI
    1.
    发明公开
    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI 审中-公开

    公开(公告)号：US20240334340A1

    公开(公告)日：2024-10-03

    申请号：US18128805

    申请日：2023-03-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Paul Blinzer ,  Chirag Nitinkumar Dhruv ,  Ranjeet Kumar ,  Gia Tung Phan ,  Ashish Jain

    IPC: H04W52/02

    CPC classification number: H04W52/029 ,  H04W52/0274

    Abstract: An apparatus and method for efficiently performing power management for increasing reliable wireless signal transfer performed by mobile computing devices. In various implementations, a computing system includes a network interface and multiple components for processing tasks. The network interface sends, to at least a given component of the multiple components, an indication specifying the corresponding operating frequency ranges used by one or more radio modules used for wireless communication with an access point. The given component determines whether an operating clock frequency of the given component overlaps any of the received operating frequency ranges and associated harmonic frequencies. If so, then the given component changes the operating clock frequency to a frequency that does not overlap any of the received operating frequency ranges and associated harmonic frequencies.

    LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT
    2.
    发明公开
    LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20240319781A1

    公开(公告)日：2024-09-26

    申请号：US18189993

    申请日：2023-03-24

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Gia Tung Phan ,  Randall Brown ,  Ashish Jain

    IPC: G06F1/3234 ,  G06F1/3228 ,  G06F1/3287

    CPC classification number: G06F1/3275 ,  G06F1/3228 ,  G06F1/3287

    Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition. The persistent on-chip memory utilizes synchronous random-access memory that receives a standby power supply reference level that continually supplies a voltage magnitude by not being turned off.

    Buffer display data in a chiplet architecture
    3.
    发明授权
    Buffer display data in a chiplet architecture 有权

    公开(公告)号：US12164365B2

    公开(公告)日：2024-12-10

    申请号：US18146811

    申请日：2022-12-27

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Gia Tung Phan ,  Ashish Jain ,  Shang Yang

    IPC: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60

    Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

    POWER MANAGEMENT OF DISPLAY DATA DURING AN IDLE SCREEN
    4.
    发明公开
    POWER MANAGEMENT OF DISPLAY DATA DURING AN IDLE SCREEN 审中-公开

    公开(公告)号：US20240331659A1

    公开(公告)日：2024-10-03

    申请号：US18128797

    申请日：2023-03-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Gia Tung Phan ,  Dennis Kin-Wah Au ,  Oswin Hall ,  Ashish Jain

    IPC: G09G5/36

    CPC classification number: G09G5/363 ,  G09G2330/021 ,  G09G2360/123

    Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple functional blocks. When control circuitry detects a low-performance mode, commands are sent to the multiple functional blocks specifying storing data of the given type in a contiguous manner in one or more of the caches of the multiple functional blocks and the memories connected to the multiple functional blocks. Following, the control circuitry transitions the memories to a sleep state and transitions all but one of the functional blocks to the sleep state. The functional blocks rotate amongst themselves with a single functional block being in the active state and servicing requests based on which data of the given type is targeted by the requests.

    BUFFER DISPLAY DATA IN A CHIPLET ARCHITECTURE
    7.
    发明公开
    BUFFER DISPLAY DATA IN A CHIPLET ARCHITECTURE 审中-公开

    公开(公告)号：US20240211023A1

    公开(公告)日：2024-06-27

    申请号：US18146811

    申请日：2022-12-27

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Gia Tung Phan ,  Ashish Jain ,  Shang Yang

    IPC: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60

    CPC classification number: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/45

    Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

    DYNAMIC REALLOCATION OF DISPLAY MEMORY BANDWIDTH BASED ON SYSTEM STATE
    9.
    发明申请
    DYNAMIC REALLOCATION OF DISPLAY MEMORY BANDWIDTH BASED ON SYSTEM STATE 有权

    公开(公告)号：US20240403242A1

    公开(公告)日：2024-12-05

    申请号：US18327813

    申请日：2023-06-01

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Gia Tung Phan ,  Shang Yang

    IPC: G06F13/16 ,  G06F13/18

    Abstract: An apparatus and method for efficiently managing memory bandwidth within a communication fabric. A computing system includes multiple clients, a display controller, and a communication fabric that transfers data between the multiple clients, the display controller, and a memory subsystem. A control circuit with power management circuitry determines that one or more conditions are satisfied for changing a power-performance state (P-state) of the memory subsystem. The control circuit asserts indications on a sideband interface specifying to the communication fabric that the display controller is to have an increased bandwidth of data transfer between the display controller and the memory subsystem. Using the increased bandwidth provided by the communication fabric, the display controller prefetches display data from a frame buffer of the memory subsystem prior to the P-state change. Afterward, the memory subsystem performs the P-state change and the corresponding training of the memory interface.

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