Adjustment of write timing in a memory device
    1.
    发明授权
    Adjustment of write timing in a memory device 有权
    调整存储设备中的写入时序

    公开(公告)号:US09508408B2

    公开(公告)日:2016-11-29

    申请号:US14243283

    申请日:2014-04-02

    Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

    Abstract translation: 提供了一种用于调整存储器件中的写时序的方法和系统。 例如,该方法可以包括接收数据信号,写时钟信号和参考信号。 该方法还可以包括随时间检测参考信号中的相移。 参考信号的相移可用于调整数据信号和写入时钟信号之间的相位差,其中存储器件基于数据信号和写入时钟信号的调整的写入定时从数据信号中恢复数据 。

    METHOD TO CONTROL SLEW RATE OF A CURRENT-MODE LOGIC OUTPUT DRIVER
    2.
    发明申请
    METHOD TO CONTROL SLEW RATE OF A CURRENT-MODE LOGIC OUTPUT DRIVER 有权
    控制电流模式逻辑输出驱动器的频率的方法

    公开(公告)号:US20140077836A1

    公开(公告)日:2014-03-20

    申请号:US14025900

    申请日:2013-09-13

    CPC classification number: H03K5/01 H04L25/0272 H04L25/0282

    Abstract: A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input data in accordance with the selected at least one of a plurality of slew rate control settings and sending output data at the data transmission speed. Also provided is data driver device that includes at least one activation portion comprising one or more slew rate controls, a voltage-mode driver portion and at least a first current-mode driver portion. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the data driver device. Also provided is a system including the data driver device, a data storage device and a processor device.

    Abstract translation: 提供了一种至少根据数据传输的速度选择多个转换速率控制设置中的至少一个并接收以数据传输速度接收输入数据的输入数据的方法。 该方法还包括根据所选择的多个转换速率控制设置中的至少一个切换所接收的输入数据,并以数据传输速度发送输出数据。 还提供了数据驱动器装置,其包括至少一个包括一个或多个转换速率控制的激活部分,电压模式驱动器部分和至少第一电流模式驱动器部分。 还提供了一种用数据编码的计算机可读存储设备,用于使制造设施适配以创建数据驱动器设备。 还提供了包括数据驱动器装置,数据存储装置和处理器装置的系统。

    Method to control slew rate of a current-mode logic output driver
    3.
    发明授权
    Method to control slew rate of a current-mode logic output driver 有权
    控制电流模式逻辑输出驱动器的转换速率的方法

    公开(公告)号:US09065428B2

    公开(公告)日:2015-06-23

    申请号:US14025900

    申请日:2013-09-13

    CPC classification number: H03K5/01 H04L25/0272 H04L25/0282

    Abstract: A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input data in accordance with the selected at least one of a plurality of slew rate control settings and sending output data at the data transmission speed. Also provided is data driver device that includes at least one activation portion comprising one or more slew rate controls, a voltage-mode driver portion and at least a first current-mode driver portion. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the data driver device. Also provided is a system including the data driver device, a data storage device and a processor device.

    Abstract translation: 提供了一种至少根据数据传输的速度选择多个转换速率控制设置中的至少一个并接收以数据传输速度接收输入数据的输入数据的方法。 该方法还包括根据所选择的多个转换速率控制设置中的至少一个切换所接收的输入数据,并以数据传输速度发送输出数据。 还提供了数据驱动器装置,其包括至少一个包括一个或多个转换速率控制的激活部分,电压模式驱动器部分和至少第一电流模式驱动器部分。 还提供了一种用数据编码的计算机可读存储设备,用于使制造设施适配以创建数据驱动器设备。 还提供了包括数据驱动器装置,数据存储装置和处理器装置的系统。

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