公开(公告)号：US20240168639A1

公开(公告)日：2024-05-23

申请号：US17990092

申请日：2022-11-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SHAIZEEN AGA ,  JOHNATHAN ALSOP ,  NUWAN JAYASENA

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus for performing distributed reduction operations using near-memory computation includes memory and a first near-memory compute node. The first-near-memory compute node is coupled to a plurality of near-memory compute nodes. The first near-memory compute node comprises logic to store first data loaded from a second near-memory compute node, perform a reduction operation on the first data and second data to compute a result; and store the result within the first near-memory compute node. In some aspects, the near-memory compute node includes a PIM execution unit and carries out the reduction operation utilizing PIM commands.

公开(公告)号：US20240220164A1

公开(公告)日：2024-07-04

申请号：US18604585

申请日：2024-03-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SOORAJ PUTHOOR ,  MUHAMMAD AMBER HASSAAN ,  ASHWIN AJI ,  MICHAEL L. CHU ,  NUWAN JAYASENA

IPC: G06F3/06 ,  G06F7/575

CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0631 ,  G06F3/0656 ,  G06F3/0679 ,  G06F7/575

Abstract: Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

公开(公告)号：US20220414013A1

公开(公告)日：2022-12-29

申请号：US17361145

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  ALEXANDRU DUTU ,  SHAIZEEN AGA ,  NUWAN JAYASENA

IPC: G06F12/0871 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/02

Abstract: Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.

公开(公告)号：US20240160364A1

公开(公告)日：2024-05-16

申请号：US17986623

申请日：2022-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ALEXANDRU DUTU ,  NUWAN JAYASENA ,  YASUKO ECKERT ,  NITI MADAN ,  SOORAJ PUTHOOR

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus includes a memory controller that includes logic to receive a first memory request having a first request type and a second memory request having a second request type. The apparatus also includes a scheduling unit that includes logic to schedule an order of the first and second memory requests for execution based upon a first parameter value and a second parameter value. The first parameter value corresponds to a utility and energy cost for the first memory request and the second parameter value corresponds to a utility and energy cost for the second memory request.

公开(公告)号：US20240045606A1

公开(公告)日：2024-02-08

申请号：US18492081

申请日：2023-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  NUWAN JAYASENA ,  SHAIZEEN AGA ,  ANDREW M. MCCRABB

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data is communicated over the memory channel.

公开(公告)号：US20210326063A1

公开(公告)日：2021-10-21

申请号：US16848920

申请日：2020-04-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ANIRBAN NAG ,  NUWAN JAYASENA ,  SHAIZEEN AGA

IPC: G06F3/06 ,  G06F9/448 ,  G06F9/48

Abstract: Memory operations using compound memory commands, including: receiving, by a memory module, a compound memory command indicating one or more operations to be applied to each portion of a plurality of portions of contiguous memory in the memory module; generating, based on the compound memory command, a plurality of memory commands to apply the one or more operations to each portion of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

公开(公告)号：US20230195645A1

公开(公告)日：2023-06-22

申请号：US17556431

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SOORAJ PUTHOOR ,  MUHAMMAD AMBER HASSAAN ,  ASHWIN AJI ,  MICHAEL L. CHU ,  NUWAN JAYASENA

IPC: G06F12/1009 ,  G06F12/1045 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/1009 ,  G06F12/1054 ,  G06F12/1063 ,  G06F12/0238 ,  G06F13/1673 ,  G06F2212/7201

Abstract: Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.

公开(公告)号：US20230077933A1

公开(公告)日：2023-03-16

申请号：US17474372

申请日：2021-09-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHN KALAMATIANOS ,  NUWAN JAYASENA

IPC: G06F9/50 ,  G06F9/46

Abstract: A processor for supporting PIM (Processing-in-Memory) execution in a multiprocessing environment includes logic configured to: receive a request to initiate an offload of a number of PIM instructions to a PIM device. The request is issued by a first thread of a processor. The logic is also configured to reserve, based on information in the request, resources of the PIM device for execution of the plurality of instructions.

公开(公告)号：US20220207643A1

公开(公告)日：2022-06-30

申请号：US17134904

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SOORAJ PUTHOOR ,  BRADFORD BECKMANN ,  NUWAN JAYASENA ,  ANTHONY GUTIERREZ

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/54 ,  G06F9/38

Abstract: Implementing heterogenous wavefronts on a graphics processing unit (GPU) is disclosed. A schedule assigns heterogeneous wavefronts for execution on a compute unit of a processing device. The heterogeneous wavefronts include different types of wavefronts such as vector compute wavefronts service-level wavefronts that vary in resource requirements and instruction sets. As one example, heterogenous wavefronts may include scalar wavefronts and vector compute wavefronts that execute on scalar units and vector units, respectively. Distinct sets of instructions are executed for the heterogenous wavefronts on the compute unit. Heterogenous wavefronts are processed in the same pipeline of the processing device.

公开(公告)号：US20210313248A1

公开(公告)日：2021-10-07

申请号：US17353115

申请日：2021-06-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： MANISH ARORA ,  NUWAN JAYASENA

IPC: H01L23/427 ,  H05K1/02

Abstract: Various circuit board embodiments are disclosed. In one aspect, an apparatus is provided that includes a circuit board and a first phase change material pocket positioned on or in the circuit board and contacting a surface of the circuit board.