公开(公告)号：US20220414013A1

公开(公告)日：2022-12-29

申请号：US17361145

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  ALEXANDRU DUTU ,  SHAIZEEN AGA ,  NUWAN JAYASENA

IPC: G06F12/0871 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/02

Abstract: Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.

公开(公告)号：US20240045606A1

公开(公告)日：2024-02-08

申请号：US18492081

申请日：2023-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  NUWAN JAYASENA ,  SHAIZEEN AGA ,  ANDREW M. MCCRABB

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data is communicated over the memory channel.

公开(公告)号：US20210326063A1

公开(公告)日：2021-10-21

申请号：US16848920

申请日：2020-04-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ANIRBAN NAG ,  NUWAN JAYASENA ,  SHAIZEEN AGA

IPC: G06F3/06 ,  G06F9/448 ,  G06F9/48

Abstract: Memory operations using compound memory commands, including: receiving, by a memory module, a compound memory command indicating one or more operations to be applied to each portion of a plurality of portions of contiguous memory in the memory module; generating, based on the compound memory command, a plurality of memory commands to apply the one or more operations to each portion of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

公开(公告)号：US20220206901A1

公开(公告)日：2022-06-30

申请号：US17136549

申请日：2020-12-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SHRIKANTH GANAPATHY ,  ROSS V. LA FETRA ,  JOHN KALAMATIANOS ,  SUDHANVA GURUMURTHI ,  SHAIZEEN AGA ,  VILAS SRIDHARAN ,  MICHAEL IGNATOWSKI ,  NUWAN JAYASENA

IPC: G06F11/14 ,  G06F11/10

Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.

公开(公告)号：US20220100606A1

公开(公告)日：2022-03-31

申请号：US17033398

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： SUDHANVA GURUMURTHI ,  VILAS SRIDHARAN ,  SHAIZEEN AGA ,  NUWAN JAYASENA ,  MICHAEL IGNATOWSKI ,  SHRIKANTH GANAPATHY ,  JOHN KALAMATIANOS

IPC: G06F11/10 ,  H04L9/32 ,  G06F21/60

Abstract: A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.

公开(公告)号：US20210303355A1

公开(公告)日：2021-09-30

申请号：US16828190

申请日：2020-03-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ANIRBAN NAG ,  NUWAN JAYASENA ,  SHAIZEEN AGA

IPC: G06F9/50 ,  G06F9/54 ,  G06F12/0882 ,  G06F12/02 ,  G06F12/1027

Abstract: Memory allocation for processing-in-memory operations, including: receiving, by an allocation module, a memory allocation request indicating a plurality of data structure operands for a processing-in-memory operation; determining a memory allocation pattern for the plurality of data structure operands, wherein the memory allocation pattern interleaves a plurality of component pages of a memory page across the plurality of data structure operands; and allocating the memory page based on the determined memory allocation pattern.

公开(公告)号：US20240168639A1

公开(公告)日：2024-05-23

申请号：US17990092

申请日：2022-11-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SHAIZEEN AGA ,  JOHNATHAN ALSOP ,  NUWAN JAYASENA

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus for performing distributed reduction operations using near-memory computation includes memory and a first near-memory compute node. The first-near-memory compute node is coupled to a plurality of near-memory compute nodes. The first near-memory compute node comprises logic to store first data loaded from a second near-memory compute node, perform a reduction operation on the first data and second data to compute a result; and store the result within the first near-memory compute node. In some aspects, the near-memory compute node includes a PIM execution unit and carries out the reduction operation utilizing PIM commands.

公开(公告)号：US20220318085A1

公开(公告)日：2022-10-06

申请号：US17536817

申请日：2021-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  SHAIZEEN AGA

IPC: G06F11/07 ,  G06F11/24 ,  G06F11/14

Abstract: Detecting execution hazards in offloaded operations is disclosed. A second offload operation is compared to a first offload operation that precedes the second offload operation. It is determined whether the second offload operation creates an execution hazard on an offload target device based on the comparison of the second offload operation to the first offload operation. If the execution hazard is detected, an error handling operation may be performed. In some examples, the offload operations are processing-in-memory operations.

公开(公告)号：US20220318015A1

公开(公告)日：2022-10-06

申请号：US17218994

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  SHAIZEEN AGA

IPC: G06F9/32 ,  G06F9/38

Abstract: Enforcing data placement requirements via address bit swapping, including: receiving an instruction comprising a first memory address associated with a first address bit mapping; generating a remapped instruction by rearranging a plurality of bits of the first memory address according to a second address bit mapping; and issuing the remapped instruction to memory.