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公开(公告)号：US11869140B2
公开(公告)日：2024-01-09
申请号：US17234692
申请日：2021-04-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Mangesh P. Nijasure , Randy W. Ramsey , Todd Martin
CPC classification number: G06T15/80 , G06T15/005
Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.
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公开(公告)号：US20230376318A1
公开(公告)日：2023-11-23
申请号：US18363333
申请日：2023-08-01
Applicant: Advanced Micro Devices, Inc.
Inventor： Todd Martin , Tad Robert Litwiller , Nishank Pathak , Randy Wayne Ramsey
IPC: G06F9/4401 , G06F9/30 , G06F9/54
CPC classification number: G06F9/4411 , G06F9/3009 , G06F9/544
Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.
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公开(公告)号：US11715262B2
公开(公告)日：2023-08-01
申请号：US16221916
申请日：2018-12-17
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Brian J. Favela , Todd Martin , Mangesh P. Nijasure
CPC classification number: G06T17/10 , G06F9/3877 , G06T1/20 , G06T15/005
Abstract: A method of deferred vertex attribute shading includes computing, at a graphics processing pipeline of a graphics processing unit (GPU), a plurality of vertex attributes for vertices of each primitive of a set of primitives. The plurality of vertex attributes to be computed includes a vertex position attribute and at least a first non-position attribute for each primitive. One or more primitives of the set of primitives that do not contribute to a rendered image are discarded based upon the vertex position attribute for vertices of the set of primitives. A set of surviving primitives is generated based on the culling and deferred attribute shading is performed for at least a second non-position attribute for vertices of the set of surviving primitives.
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公开(公告)号：US20230097097A1
公开(公告)日：2023-03-30
申请号：US17489105
申请日：2021-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Todd Martin , Tad Robert Litwiller , Nishank Pathak , Randy Wayne Ramsey , Michael J. Mantor , Christopher J. Brennan , Mark M. Leather , Ryan James Cash
Abstract: Systems, apparatuses, and methods for preemptively reserving buffer space for primitives and positions in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with any number of geometry engines coupled to corresponding shader engines. Each geometry engine launches shader wavefronts to execute on a corresponding shader engine. The geometry engine preemptively reserves buffer space for each wavefront prior to the wavefront being launched on the shader engine. When the shader engine executes a wavefront, the shader engine exports primitive and position data to the reserved buffer space. Multiple scan converters will consume the primitive and position data, with each scan converter consuming primitive and position data based on the screen coverage of the scan converter. After consuming the primitive and position data, the scan converters mark the buffer space as freed so that the geometry engine can then allocate the freed buffer space to subsequent shader wavefronts.
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公开(公告)号：US20230094115A1
公开(公告)日：2023-03-30
申请号：US17489008
申请日：2021-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Todd Martin , Tad Robert Litwiller , Nishank Pathak , Randy Wayne Ramsey
IPC: G06T15/00
Abstract: Systems, apparatuses, and methods for loading multiple primitives per thread in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with a geometry engine, shader processor input (SPI), and a plurality of compute units. The geometry engine generates primitives which are accumulated by the SPI into primitive groups. While accumulating primitives, the SPI tracks the number of vertices and primitives per group. The SPI determines wavefront boundaries based on mapping a single vertex to each thread of the wavefront while allowing more than one primitive per thread. The SPI launches wavefronts with one vertex per thread and potentially multiple primitives per thread. The compute units execute a vertex phase and a multi-cycle primitive phase for wavefronts with multiple primitives per thread.
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Patent Agency Ranking
公开(公告)号：US11532066B2
公开(公告)日：2022-12-20
申请号：US17318523
申请日：2021-05-12
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mangesh P. Nijasure , Tad Litwiller , Todd Martin , Nishank Pathak
Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.
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公开(公告)号：US11010862B1
公开(公告)日：2021-05-18
申请号：US16683868
申请日：2019-11-14
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mangesh P. Nijasure , Tad Litwiller , Todd Martin , Nishank Pathak
Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.
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公开(公告)号：US10217280B2
公开(公告)日：2019-02-26
申请号：US15354513
申请日：2016-11-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Saad Arrabi , Mangesh P. Nijasure , Todd Martin
Abstract: Techniques for removing reset indices from, and identifying primitives in, an index stream that defines a set of primitives to be rendered, are disclosed. The index stream may be specified by an application program executing on the central processing unit. The technique involves classifying the primitive topology for the index stream as either requiring an offset-based technique or requiring a non-offset-based technique. This classification is done by determining whether, according to the primitive topology, each subsequent index can form a primitive with prior indices (e.g., line strip, triangle strip). If each subsequent index can form a primitive with prior indices, then the technique used is the non-offset-based technique. If each subsequent index does not form a primitive with prior indices, but instead at least two indices are required to form a new primitive (e.g., line list, triangle list), then the technique used is the offset-based technique.
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公开(公告)号：US10049487B2
公开(公告)日：2018-08-14
申请号：US15360395
申请日：2016-11-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Saad Arrabi , Mangesh P. Nijasure , Todd Martin
Abstract: Techniques for removing duplicate indices from an index stream are disclosed. The techniques involve dividing the indices into chunks. For any particular chunk, the techniques involve examining each index in the chunk to determine whether a “match” exists for that index within a reuse depth sliding window. The reuse depth sliding window includes a fixed number of indices immediately prior to the index being examined for a match. If a match exists, then the index is marked as non-unique and is assigned a position value equal to the position value of the matching index. If a match does not exist, then the index is marked as unique and assigned the next available position value for the chunk. After assigning position values to indices in a chunk, the indices in the chunk are transmitted to a vertex shader stage for processing in the order indicated by the position values.
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公开(公告)号：US12169896B2
公开(公告)日：2024-12-17
申请号：US17489105
申请日：2021-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Todd Martin , Tad Robert Litwiller , Nishank Pathak , Randy Wayne Ramsey , Michael J. Mantor , Christopher J. Brennan , Mark M. Leather , Ryan James Cash
Abstract: Systems, apparatuses, and methods for preemptively reserving buffer space for primitives and positions in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with any number of geometry engines coupled to corresponding shader engines. Each geometry engine launches shader wavefronts to execute on a corresponding shader engine. The geometry engine preemptively reserves buffer space for each wavefront prior to the wavefront being launched on the shader engine. When the shader engine executes a wavefront, the shader engine exports primitive and position data to the reserved buffer space. Multiple scan converters will consume the primitive and position data, with each scan converter consuming primitive and position data based on the screen coverage of the scan converter. After consuming the primitive and position data, the scan converters mark the buffer space as freed so that the geometry engine can then allocate the freed buffer space to subsequent shader wavefronts.
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