公开(公告)号：US20210232501A1

公开(公告)日：2021-07-29

申请号：US16776416

申请日：2020-01-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Weon Taek Na ,  Yasuko Eckert ,  Mark H. Oskin ,  Gabriel H. Loh ,  William Louie Walker ,  Michael Warren Boyer

IPC: G06F12/0815 ,  G06F16/22

Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.

公开(公告)号：US20240411692A1

公开(公告)日：2024-12-12

申请号：US18332112

申请日：2023-06-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Hsiuwei Loh ,  Joseph Lee Greathouse ,  William Louie Walker ,  Paul James Moyer

IPC: G06F12/0802

Abstract: Cache replacement policies are described. In accordance with the described techniques, a request for data is received and a cache replacement policy controls how a controller responds to the request. The cache replacement policy assigns each cacheline a priority value, which indicates whether the cacheline should be preserved relative to other cachelines, in response to the request being a cache miss that necessitates eviction of at least one cacheline. The cache replacement policy decrements priority values until at least one cacheline achieves a minimum priority value, at which point a cacheline is evicted. The cache replacement policy designates certain cachelines as protected, either via a separate protected indicator or via the cacheline's priority value, which causes unprotected cachelines to be selected for eviction while favoring preservation of protected cachelines in the cache.

公开(公告)号：US20220100686A1

公开(公告)日：2022-03-31

申请号：US17548385

申请日：2021-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Bryan P. Broussard ,  Paul James Moyer ,  William Louie Walker

IPC: G06F13/24 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

公开(公告)号：US11226900B2

公开(公告)日：2022-01-18

申请号：US16776416

申请日：2020-01-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Weon Taek Na ,  Yasuko Eckert ,  Mark H. Oskin ,  Gabriel H. Loh ,  William Louie Walker ,  Michael Warren Boyer

IPC: G06F12/0815 ,  G06F16/22 ,  G06F12/0831

Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.

公开(公告)号：US11210246B2

公开(公告)日：2021-12-28

申请号：US16112367

申请日：2018-08-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Bryan P. Broussard ,  Paul James Moyer ,  William Louie Walker

IPC: G06F13/24 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

公开(公告)号：US20240202116A1

公开(公告)日：2024-06-20

申请号：US18068930

申请日：2022-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  John Kalamatianos ,  Paul James Moyer ,  Nicholas Dean Lance ,  Sriram Srinivasan ,  Patrick James Shyvers ,  William Louie Walker

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/1044

Abstract: An entry of a last level cache shadow tag array to track pending last level cache misses to private data in a previous level cache (e.g., an L2 cache), that also are misses to an exclusive last level cache (e.g., an L3 cache) and to the last level cache shadow tag array. Accordingly, last level cache miss status holding registers need not be expended to track cache misses to private data that are already being tracked by a previous level cache miss status holding register. Additionally or alternatively, up to a threshold number of last level cache pending misses to the same shared data from different processor cores are tracked in the last level cache shadow tag array, and any additional last level cache pending misses are tracked in a last level cache miss status holding register.

公开(公告)号：US20200065275A1

公开(公告)日：2020-02-27

申请号：US16112367

申请日：2018-08-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Bryan P. Broussard ,  Paul James Moyer ,  William Louie Walker

IPC: G06F13/24 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

公开(公告)号：US20170357585A1

公开(公告)日：2017-12-14

申请号：US15180828

申请日：2016-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer ,  William Louie Walker ,  Sriram Srinivasan

IPC: G06F12/0811 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/084 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/602 ,  G06F2212/6042

Abstract: A processor replaces data at a first cache based on hints from a second cache, wherein the hints indicate information about the data that is not available to the first cache directly. When data at an entry is transferred from the first cache to the second cache, the first cache can provide an age hint to the second cache to indicate that the data should be assigned a higher or lower initial age relative to a nominal initial age. The second cache assigns the entry for the data an initial age based on the age hint and, when replacing data, selects data for replacement based on the age of each entry.