公开(公告)号：US20230307380A1

公开(公告)日：2023-09-28

申请号：US17705216

申请日：2022-03-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan LIN ,  Ming-Chiang LEE ,  Yung-I YEH

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L25/18 ,  H01L23/5385 ,  H01L24/48 ,  H01L2224/48145

Abstract: A semiconductor device package is disclosed. The semiconductor device package includes a carrier, a first electronic component disposed on the carrier and a support component disposed on the carrier. The semiconductor device package also includes a second electronic component disposed on the first electronic component and supported by the support component.

公开(公告)号：US20230361060A1

公开(公告)日：2023-11-09

申请号：US18223525

申请日：2023-07-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan LIN ,  Wei-Tung CHANG ,  Jen-Chieh KAO ,  Huei-Shyong CHO

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01Q1/22 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01Q1/2283 ,  H01L24/16 ,  H01Q1/243

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

公开(公告)号：US20210305181A1

公开(公告)日：2021-09-30

申请号：US17347220

申请日：2021-06-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan LIN ,  Wei-Tung CHANG ,  Jen-Chieh KAO ,  Huei-Shyong CHO

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01Q1/22 ,  H01L23/00

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

公开(公告)号：US20200273823A1

公开(公告)日：2020-08-27

申请号：US16287962

申请日：2019-02-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsiang Chi CHEN ,  Cheng-Nan LIN

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/78 ,  H01Q1/22

Abstract: A semiconductor device package includes a first substrate, a second substrate, an electrical contact and a support element. The first substrate has a first surface. The second substrate has a first surface facing the first surface of the first substrate. The electrical contact is disposed between the first substrate and the second substrate. The support element is disposed between the first substrate and the second substrate. The support element includes a thermosetting material.

公开(公告)号：US20200098709A1

公开(公告)日：2020-03-26

申请号：US16453780

申请日：2019-06-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan LIN ,  Wei-Tung CHANG ,  Jen-Chieh KAO ,  Huei-Shyong CHO

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01Q1/22

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

公开(公告)号：US20170200682A1

公开(公告)日：2017-07-13

申请号：US14990366

申请日：2016-01-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： I-Chia LIN ,  Chieh-Chen FU ,  Kuo Hsien LIAO ,  Cheng-Nan LIN

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81

Abstract: A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top surface of the carrier and covering the electronic component. The semiconductor device package further includes a shield layer, which in turn includes a first electrically conductive layer, a first magnetically permeable layer, and a second electrically conductive layer, where the first magnetically permeable layer is interposed between and directly contacts the first electrically conductive layer and the second electrically conductive layer.

公开(公告)号：US20170005042A1

公开(公告)日：2017-01-05

申请号：US14791043

申请日：2015-07-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shih-Ren CHEN ,  Cheng-Nan LIN

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00012

Abstract: The present disclosure relates to a semiconductor device package and a method for manufacturing the semiconductor device package. The semiconductor device package includes a substrate, a grounding element, a component, a package body and a conductive layer. The grounding element is disposed in the substrate and includes a connection surface exposed at a second portion of a lateral surface of the substrate. The component is disposed on a top surface of the substrate. The package body covers the component and the top surface of the substrate. A lateral surface of the package body is aligned with the lateral surface of the substrate. The conductive layer covers a top surface and the lateral surface of the package body, and further covers the second portion of the lateral surface of the substrate. A first portion of the lateral surface of the substrate is exposed from the conductive layer.

Abstract translation: 本发明涉及半导体器件封装以及半导体器件封装的制造方法。 半导体器件封装包括衬底，接地元件，部件，封装体和导电层。 接地元件设置在基板中，并且包括暴露在基板的侧表面的第二部分处的连接表面。 该部件设置在基板的顶表面上。 封装体覆盖基板的部件和顶表面。 封装体的侧表面与衬底的侧表面对齐。 导电层覆盖封装主体的顶表面和侧表面，并且还覆盖基板的侧表面的第二部分。 衬底的侧表面的第一部分从导电层露出。

公开(公告)号：US20250038136A1

公开(公告)日：2025-01-30

申请号：US18916604

申请日：2024-10-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan LIN ,  Wei-Tung CHANG ,  Jen-Chieh KAO ,  Huei-Shyong CHO

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01Q1/22 ,  H01Q1/24

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

公开(公告)号：US20210343664A1

公开(公告)日：2021-11-04

申请号：US16862455

申请日：2020-04-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wei-Tung CHANG ,  Cheng-Nan LIN

IPC: H01L23/66 ,  H01L23/48 ,  H01Q1/22

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first electronic component having an active surface and a backside surface opposite to the active surface and a first antenna layer disposed on the backside surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer. A method of manufacturing a semiconductor device package is also disclosed.

公开(公告)号：US20210111134A1

公开(公告)日：2021-04-15

申请号：US16653644

申请日：2019-10-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wei-Tung CHANG ,  Cheng-Nan LIN

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498

Abstract: An electronic device package includes a first conductive substrate, a second conductive substrate and a dielectric layer. The first conductive substrate has a first coefficient of thermal expansion (CTE). The second conductive substrate is disposed on an upper surface of the first conductive substrate and electrically connected to the first conductive substrate. The second conductive substrate has a second CTE. The dielectric layer is disposed on the upper surface of the first conductive substrate and disposed on at least one sidewall of the second conductive substrate. The dielectric layer has a third CTE. A difference between the first CTE and the second CTE is larger than a difference between the first CTE and the third CTE.