公开(公告)号：US20210090965A1

公开(公告)日：2021-03-25

申请号：US16578088

申请日：2019-09-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Hsu-Chiang SHIH ,  Cheng-Yuan KUNG ,  Hung-Yi LIN

IPC: H01L23/28 ,  H01L21/56 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.

公开(公告)号：US20190057809A1

公开(公告)日：2019-02-21

申请号：US15680059

申请日：2017-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Hung-Yi LIN ,  Teck-Chong LEE ,  Sheng-Chi HSIEH ,  Chien-Hua CHEN

IPC: H01F27/40 ,  H01F21/12 ,  H01F27/28 ,  H01F27/29 ,  H03H7/38 ,  H01L25/16

Abstract: An electrical device comprises a substrate, a first dielectric layer, a first die, an adjustable inductor and a second die. The substrate has a first surface. The first dielectric layer is disposed on the first surface of the substrate and has a first surface. The first die is surrounded by the first dielectric layer. The adjustable inductor is electrically connected to the first die. The adjustable inductor comprises a plurality of pillars surrounded by the first dielectric layer, a plurality of first metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars, and a plurality of second metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars. A width of at least one of the second metal strips is different than a width of at least one of the first metal strips. The second die is electrically connected to the adjustable inductor.

公开(公告)号：US20230075336A1

公开(公告)日：2023-03-09

申请号：US17987693

申请日：2022-11-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Cheng-Yuan KUNG

IPC: H01L25/10 ,  H01L41/047 ,  H01L41/053 ,  H03H9/64 ,  H01L41/23 ,  H01L41/25 ,  H03H9/60 ,  H01L23/522

Abstract: A semiconductor package structure includes a plurality of transducer devices, a cap structure, at least one redistribution layer (RDL) and a protection material. The transducer devices are disposed side by side. Each of the transducer devices has at least one transducing region, and includes a die body and at least one transducing element. The die body has a first surface and a second surface opposite to the first surface. The transducing region is disposed adjacent to the first surface of the die body. The transducing element is disposed adjacent to the first surface of the die body and within the transducing region. The cap structure covers the transducing region of the transducer device to form an enclosed space. The redistribution layer (RDL) electrically connects the transducer devices. The protection material covers the transducer devices.

公开(公告)号：US20200083591A1

公开(公告)日：2020-03-12

申请号：US16544415

申请日：2019-08-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Chi HSIEH ,  Chen-Chao WANG ,  Teck-Chong LEE ,  Chien-Hua CHEN

IPC: H01Q1/22 ,  H01L23/15 ,  H01L23/498 ,  H01L23/00 ,  H01L23/66 ,  H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01Q9/16

Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.

公开(公告)号：US20200075571A1

公开(公告)日：2020-03-05

申请号：US16560870

申请日：2019-09-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/66

Abstract: A semiconductor device package includes a carrier, an electronic component, a protection layer, a conductive layer and an integrated passive device (IPD). The electronic component is disposed on the carrier. The protection layer covers the carrier and the electronic component. The conductive layer is disposed on the protection layer and penetrates the protection layer to be electrically connected to the electronic component. The IPD is disposed on the conductive layer and electrically connected to the electronic component through the conductive layer.

公开(公告)号：US20180337164A1

公开(公告)日：2018-11-22

申请号：US15599379

申请日：2017-05-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Hung-Yi LIN ,  Cheng-Yuan KUNG ,  Teck-Chong LEE ,  Shiuan-Yu LIN

IPC: H01L25/16 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31

Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.

公开(公告)号：US20230261036A1

公开(公告)日：2023-08-17

申请号：US18139348

申请日：2023-04-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L27/08 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/642

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

公开(公告)号：US20200335858A1

公开(公告)日：2020-10-22

申请号：US16388828

申请日：2019-04-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Sheng-Chi HSIEH ,  Chen-Chao WANG ,  Teck-Chong LEE

IPC: H01Q1/38 ,  H01L23/15 ,  H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/13 ,  H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01Q23/00

Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.

公开(公告)号：US20180138113A1

公开(公告)日：2018-05-17

申请号：US15352529

申请日：2016-11-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE ,  Yung-Shun CHANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H05K3/40 ,  H01L21/683

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device package includes a semiconductor chip, a glass substrate having a first surface facing the semiconductor chip and a second surface opposite to the first surface, the glass substrate defining a hole that traverses the glass substrate from the first surface to the second surface, an interconnect structure disposed in the hole, and a conductive bump disposed adjacent to the interconnect structure and protruded from the second surface, wherein the conductive bump and the interconnect structure include a same material.

公开(公告)号：US20170047276A1

公开(公告)日：2017-02-16

申请号：US14825326

申请日：2015-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE ,  Chi-Han CHEN ,  Sheng-Chi HSIEH

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/11

Abstract: The present disclosure relates to a semiconductor device package and a method for manufacturing the same. The semiconductor device package comprises a substrate, a first patterned conductive layer, an insulator layer, a second patterned conductive layer, and a dielectric layer. The first patterned conductive layer is disposed on a surface of the substrate. The insulator layer is disposed on the surface of the substrate and covers the first patterned conductive layer. The second patterned conductive layer is fully encapsulated by the insulator layer. The dielectric layer is disposed on the insulator layer.

Abstract translation: 本公开涉及一种半导体器件封装及其制造方法。 半导体器件封装包括衬底，第一图案化导电层，绝缘体层，第二图案化导电层和电介质层。 第一图案化导电层设置在基板的表面上。 绝缘体层设置在衬底的表面上并覆盖第一图案化导电层。 第二图案化导电层被绝缘体层完全封装。 电介质层设置在绝缘体层上。