公开(公告)号：US11018120B2

公开(公告)日：2021-05-25

申请号：US16434075

申请日：2019-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei Huang ,  Shih-Yu Wang ,  I-Ting Lin ,  Wen Hung Huang ,  Yuh-Shan Su ,  Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528 ,  H01L23/29

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US11721678B2

公开(公告)日：2023-08-08

申请号：US17330240

申请日：2021-05-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei Huang ,  Shih-Yu Wang ,  I-Ting Lin ,  Wen Hung Huang ,  Yuh-Shan Su ,  Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528 ,  H01L23/29

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/17 ,  H01L23/293 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US10522492B2

公开(公告)日：2019-12-31

申请号：US15614563

申请日：2017-06-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Chien-Mei Huang

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/14 ,  H01L23/04 ,  H01L23/498 ,  H01L21/3213

Abstract: A wiring structure includes a dielectric layer and a first patterned conductive layer on the dielectric layer. The dielectric layer has a first region and a second region. The first patterned conductive layer includes a number of fine conductive lines and a number of dummy conductive structures. The number of conductive lines include a first number of conductive lines on the first region and a second number of conductive lines on the second region, and the number of dummy conductive structures include a first number of dummy conductive structures on the second region. The first number of conductive lines occupy a first area on the first region, and the second number of conductive lines and the first number of dummy conductive structures occupy a second area on the second region. A ratio of the second area to the first area is greater than or equal to about 80%.

公开(公告)号：US12218075B2

公开(公告)日：2025-02-04

申请号：US17566575

申请日：2021-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Hsu-Chiang Shih ,  Hung-Yi Lin ,  Chien-Mei Huang

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.

公开(公告)号：US11031326B2

公开(公告)日：2021-06-08

申请号：US16802478

申请日：2020-02-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Chien-Mei Huang ,  Yan Wen Chung

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.