Semiconductor device and method for manufacturing the same

    公开(公告)号:US11784111B2

    公开(公告)日:2023-10-10

    申请号:US17334569

    申请日:2021-05-28

    摘要: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.

    Package structure and method for manufacturing the same

    公开(公告)号:US11502067B2

    公开(公告)日:2022-11-15

    申请号:US16518837

    申请日:2019-07-22

    摘要: A semiconductor package structure includes a plurality of transducer devices, a cap structure, at least one redistribution layer (RDL) and a protection material. The transducer devices are disposed side by side. Each of the transducer devices has at least one transducing region, and includes a die body and at least one transducing element. The die body has a first surface and a second surface opposite to the first surface. The transducing region is disposed adjacent to the first surface of the die body. The transducing element is disposed adjacent to the first surface of the die body and within the transducing region. The cap structure covers the transducing region of the transducer device to form an enclosed space. The redistribution layer (RDL) electrically connects the transducer devices. The protection material covers the transducer devices.

    Capacitor bank structure and semiconductor package structure

    公开(公告)号:US11545427B2

    公开(公告)日:2023-01-03

    申请号:US16447839

    申请日:2019-06-20

    摘要: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

    Assembly structure and package structure

    公开(公告)号:US11233010B2

    公开(公告)日:2022-01-25

    申请号:US16732157

    申请日:2019-12-31

    摘要: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section. The second signal transmission path is between the second surface of the sub-computing section and the at least one conductive via of the sub-computing section.