公开(公告)号：US11037846B2

公开(公告)日：2021-06-15

申请号：US16578088

申请日：2019-09-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Hsu-Chiang Shih ,  Cheng-Yuan Kung ,  Hung-Yi Lin

IPC: H01L21/56 ,  H01L23/28 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.

公开(公告)号：US12218075B2

公开(公告)日：2025-02-04

申请号：US17566575

申请日：2021-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Hsu-Chiang Shih ,  Hung-Yi Lin ,  Chien-Mei Huang

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.

公开(公告)号：US09881917B2

公开(公告)日：2018-01-30

申请号：US14801730

申请日：2015-07-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Hsu-Chiang Shih ,  Sheng-Chi Hsieh ,  Chien-Hua Chen ,  Teck-Chong Lee

IPC: H01L27/10 ,  H01L23/48 ,  H01G4/30 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01G4/30 ,  H01L23/481 ,  H01L27/101 ,  H01L28/60 ,  H01L2224/18

Abstract: A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.

公开(公告)号：US20220157709A1

公开(公告)日：2022-05-19

申请号：US16951936

申请日：2020-11-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Chiang Shih ,  Meng-Wei Hsieh ,  Hung-Yi Lin ,  Cheng-Yuan Kung

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L27/08 ,  H01L21/768 ,  H01L21/78

Abstract: A semiconductor package structure and method for manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a conductive pillar, a second electronic component, and a conductive through via. The conductive pillar is disposed on the first electronic component and has a first surface facing away from the first electronic component. The second electronic component is disposed on the first electronic component. The conductive through via extends through the second electronic component and has a first surface facing away from the first electronic component. The first surface of the conductive through via and the first surface of the conductive pillar are substantially coplanar.

公开(公告)号：US11342282B2

公开(公告)日：2022-05-24

申请号：US16798170

申请日：2020-02-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Chiang Shih ,  Hung-Yi Lin ,  Meng-Wei Hsieh ,  Yu Sheng Chang ,  Hsiu-Chi Liu ,  Mark Gerber

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.

公开(公告)号：US10304765B2

公开(公告)日：2019-05-28

申请号：US15618084

申请日：2017-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Ming-Hung Chen ,  Hsu-Chiang Shih

IPC: H01L23/04 ,  H01L23/498 ,  H01L21/48 ,  H05K1/16 ,  H01L23/538

Abstract: A semiconductor device package includes a substrate, a first insulation layer, a support film and an interconnection structure. The substrate has a first sidewall, a first surface and a second surface opposite to the first surface. The first insulation layer is on the first surface of the substrate and has a second sidewall. The first insulation layer has a first surface and a second surface adjacent to the substrate and opposite to the first surface of the first insulation layer. The support film is on the second surface of the substrate and has a third sidewall. The support film has a first surface adjacent to the substrate and a second surface opposite to the first surface of the support film. The interconnection structure extends from the first surface of the first insulation layer to the second surface of the support film via the first insulation layer and the support film. The interconnection structure covers the first, second and third sidewalls.