公开(公告)号：US20210035912A1

公开(公告)日：2021-02-04

申请号：US16528336

申请日：2019-07-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsing Kuo TIEN ,  Chih Cheng LEE

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.

公开(公告)号：US20210343648A1

公开(公告)日：2021-11-04

申请号：US17373532

申请日：2021-07-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsing Kuo TIEN ,  Chih Cheng LEE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31

Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.

公开(公告)号：US20200350223A1

公开(公告)日：2020-11-05

申请号：US16402127

申请日：2019-05-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih Cheng LEE

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device package includes a dielectric layer, a package body and a protection structure. The dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The package body is disposed on the first surface of the dielectric layer. The package body covers a first portion of the lateral surface of the dielectric layer and exposes a second portion of the lateral surface of the dielectric layer. The protection structure is disposed on the second portion of the lateral surface of the dielectric layer.

公开(公告)号：US20210159200A1

公开(公告)日：2021-05-27

申请号：US16698671

申请日：2019-11-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor device package includes an electronic component, a first passivation layer having an inner surface surrounding the electronic component, and a conductive layer disposed on the inner surface of the first passivation layer. The electronic component has a first surface, a second surface opposite the first surface, and a lateral surface extended between the first surface and the second surface. The conductive layer has a relatively rough surface. A method of manufacturing a semiconductor device package is also disclosed.

公开(公告)号：US20190164782A1

公开(公告)日：2019-05-30

申请号：US15824919

申请日：2017-11-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih Cheng LEE

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/11622 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81192 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/013 ,  H01L2924/00014

Abstract: A semiconductor substrate includes a dielectric layer, a first patterned conductive layer and a first connection element. The dielectric layer has a first surface. The first patterned conductive layer has a first surface and is disposed adjacent to the first surface of the dielectric layer. The first connection element is disposed on the first surface of the first patterned conductive layer. The first connection element includes a first portion, a second portion and a seed layer disposed between the first portion and the second portion. The first portion of the first connection element and the first patterned conductive layer are formed to be a monolithic structure.

公开(公告)号：US20180145017A1

公开(公告)日：2018-05-24

申请号：US15356407

申请日：2016-11-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan TSAI ,  Po-Shu PENG ,  Cheng-Lin HO ,  Chih Cheng LEE

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

Abstract: A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of dielectric layers and a plurality of patterned conductive layers. A topmost patterned conductive layer of the patterned conductive layers is embedded in a topmost dielectric layer of the dielectric layers. The component is embedded in the multi-layered structure. The first conductive via is electrically connected to the component and one of the patterned conductive layers. At least one of the patterned conductive layers is located at a depth spanning between a top surface of the passive layer and a bottom surface of the component

公开(公告)号：US20190164871A1

公开(公告)日：2019-05-30

申请号：US15824913

申请日：2017-11-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng LEE ,  Yu-Lin Shih

IPC: H01L23/495 ,  H01L23/42 ,  H01L23/367 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/49568 ,  H01L21/568 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/181

Abstract: A semiconductor substrate includes a dielectric layer, a heat dissipation structure and a first patterned conductive layer. The dielectric layer has a surface. The heat dissipation structure is surrounded by the dielectric layer. The heat dissipation structure defines a space and includes a liquid in the space. The first patterned conductive layer is disposed adjacent to the surface of the dielectric layer and thermally connected with the heat dissipation structure.

公开(公告)号：US20190067211A1

公开(公告)日：2019-02-28

申请号：US15691053

申请日：2017-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng LEE ,  Yuan-Chang SU

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2221/68345 ,  H01L2221/68359 ,  H05K1/0284 ,  H05K1/0313 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/111 ,  H05K1/113 ,  H05K1/119

Abstract: A substrate for packaging a semiconductor device is disclosed. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer. The first dielectric layer includes a first portion adjacent to the first surface, a second portion adjacent to the second surface, and a reinforcement structure between the first portion and the second portion. A thickness of the first portion of the first dielectric layer is different from a thickness of the second portion of the first dielectric layer.

公开(公告)号：US20180240743A1

公开(公告)日：2018-08-23

申请号：US15439752

申请日：2017-02-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng LEE ,  Yuan-Chang SU

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/00012

Abstract: A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.