公开(公告)号：US11594506B2

公开(公告)日：2023-02-28

申请号：US17030181

申请日：2020-09-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pei-Jen Lo ,  Shun-Tsat Tu ,  Cheng-En Weng

IPC: H01L23/00

Abstract: A semiconductor package is provided. The semiconductor package includes a first conductive layer, a plurality of first conductive pads, a plurality of second conductive pads, and a first dielectric layer. The first conductive pads are electrically connected to the first conductive layer. The second conductive pads are electrically disconnected from the first conductive layer.

公开(公告)号：US10854553B1

公开(公告)日：2020-12-01

申请号：US16424228

申请日：2019-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun-Tsat Tu ,  Chunku Kuo ,  Ya-Tian Hou ,  Tsung-Chieh Kuo

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package structure includes a substrate having a patterned surface, the patterned surface including a first region and a second region, wherein a first line width in the first region is smaller than a second line width in the second region. The semiconductor package structure further includes a first die hybrid-bonded to the first region through conductive features adapted for the first line width, and a second die bonded to the second region through conductive features adapted for the second line width. The manufacturing operations of the semiconductor package structure are also disclosed.

公开(公告)号：US11538756B2

公开(公告)日：2022-12-27

申请号：US17023260

申请日：2020-09-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun-Tsat Tu ,  Pei-Jen Lo ,  Chien-Han Chiu

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L23/495

Abstract: A bonding structure is provided. The bonding structure includes a conductive layer, a seed layer, and a nanotwinned copper (NT-Cu) layer. The seed layer is disposed on the conductive layer. The NT-Cu layer is disposed on the seed layer. The NT-Cu layer has anisotropic crystal structure.

公开(公告)号：US11114370B2

公开(公告)日：2021-09-07

申请号：US16675013

申请日：2019-11-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun-Tsat Tu ,  Hong-Jyun Lin ,  Yi Tong Chiu ,  Yi Chun Wu

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, a redistribution structure, a conductive pad, a conductive element, and a conductive via. The redistribution structure is disposed over the substrate and includes a first dielectric layer and a first conductive layer. The conductive pad is disposed on a first surface of the first dielectric layer. The conductive element is disposed in the first dielectric layer and is electrically connected to the conductive pad. The conductive via extends from the conductive pad toward the substrate through the conductive element and the first dielectric layer. The first conductive layer is separated from the conductive via.

公开(公告)号：US10811347B2

公开(公告)日：2020-10-20

申请号：US16234048

申请日：2018-12-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun-Tsat Tu

IPC: H01L27/11 ,  H01L23/52 ,  H01L29/10 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor device package is provided, which includes a semiconductor device, a redistribution layer, an under bump metallurgy (UBM) structure, a passivation layer and a protection layer. The semiconductor device has an active surface. The redistribution layer is disposed on the active surface of the semiconductor device and electrically connected to the semiconductor device. The UBM structure is disposed on the redistribution layer. The passivation layer is disposed on the redistribution layer and surrounding the UBM structure and having a first surface. The protection layer is disposed on the redistribution layer and having a first surface. The first surface of the passivation layer is substantially coplanar with the first surface of the protection layer.

公开(公告)号：US11978706B2

公开(公告)日：2024-05-07

申请号：US17460051

申请日：2021-08-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun-Tsat Tu ,  Pei-Jen Lo

IPC: H01L23/544 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/20 ,  H01L24/80 ,  H01L2223/54426 ,  H01L2224/0213 ,  H01L2224/0362 ,  H01L2224/06515 ,  H01L2224/08225 ,  H01L2224/80031 ,  H01L2224/80047

Abstract: An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.

公开(公告)号：US11749593B2

公开(公告)日：2023-09-05

申请号：US17378511

申请日：2021-07-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun-Tsat Tu

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/49833 ,  H01L21/4814 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L25/50 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73265

Abstract: An electronic structure, an electronic package structure and method of manufacturing an electronic device are provided. The electronic structure includes a carrier and a protection layer. The carrier includes a first pad, a second pad and a first dielectric layer. The first pad is at a side of the carrier and configured to bond with a conductive pad. The second pad is at the side of carrier and configured to electrically connect an exterior circuit. The first dielectric layer includes a first portion around the first pad and a second portion around the second pad, wherein a top surface of the first portion and a top surface of the second portion are substantially coplanar. The protection layer is on the second pad and covers the second pad.

公开(公告)号：US11011491B2

公开(公告)日：2021-05-18

申请号：US16563701

申请日：2019-09-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun-Tsat Tu ,  Pei-Jen Lo ,  Fong Ren Sie ,  Cheng-En Weng ,  Min Lung Huang

IPC: H01L23/00

Abstract: A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.