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公开(公告)号：US07056773B2
公开(公告)日：2006-06-06
申请号：US10709323
申请日：2004-04-28
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.
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公开(公告)号：US07476946B2
公开(公告)日：2009-01-13
申请号：US11427222
申请日：2006-06-28
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.
摘要翻译： 在前栅侧和后栅极侧制造具有不同介电层厚度的背景FinFET的方法包括将杂质引入FinFET的鳍的至少一侧的步骤，以形成不同厚度的电介质层。 可以通过注入引入的杂质增强或延迟电介质形成。
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公开(公告)号：US07187042B2
公开(公告)日：2007-03-06
申请号：US11365504
申请日：2006-03-02
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.
摘要翻译： 在前栅侧和后栅极侧制造具有不同介电层厚度的背景FinFET的方法包括将杂质引入FinFET的鳍的至少一侧的步骤，以形成不同厚度的电介质层。 可以通过注入引入的杂质增强或延迟电介质形成。
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公开(公告)号：US20090261425A1
公开(公告)日：2009-10-22
申请号：US12106476
申请日：2008-04-21
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/66803 , H01L29/785
摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.
摘要翻译： 一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。 接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。 该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。 该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。
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公开(公告)号：US07994612B2
公开(公告)日：2011-08-09
申请号：US12106476
申请日：2008-04-21
IPC分类号： H01L21/02
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/66803 , H01L29/785
摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.
摘要翻译： 一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。 接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。 该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。 该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。
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公开(公告)号：US06562713B1
公开(公告)日：2003-05-13
申请号：US10078779
申请日：2002-02-19
IPC分类号： H01L214763
CPC分类号： H01L29/66545 , H01L21/823456
摘要： Disclosed is a method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma layer of a silicon compound, selected from the group silicon oxide and silicon nitride, in a manner effective in leaving an upper surface of said gate exposed. Also disclosed is a method of processing short gates while protecting long gates on a semiconductor surface, the method comprising depositing a planarizing layer of a silicon compound, selected from the group silicon nitride and silicon oxide, up to substantially the same height as said gates, and processing said semiconductor surface.
摘要翻译： 公开了一种保护半导体区域同时暴露栅极以在半导体表面上进行处理的方法，该方法包括以有效离开的方式沉积选自硅氧化物和氮化硅的硅化合物的平面化高密度等离子体层 所述门的上表面暴露。 还公开了一种处理短栅极同时保护半导体表面上的长栅极的方法，该方法包括沉积选自氮化硅和氧化硅的硅化合物的平坦化层，其高达与所述栅极基本相同的高度， 并处理所述半导体表面。
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7.发明授权High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture 有权使用Si：C和SiGe外延源/漏极的高性能应力增强型MOSFET及其制造方法公开(公告)号：US09023698B2
公开(公告)日：2015-05-05
申请号：US13446609
申请日：2012-04-13
IPC分类号： H01L21/8238 , H01L29/78 , H01L29/10 , H01L29/66 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/3081 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.
摘要翻译： 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。
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公开(公告)号：US07696025B2
公开(公告)日：2010-04-13
申请号：US11867840
申请日：2007-10-05
申请人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
CPC分类号： H01L29/785 , H01L29/1083 , H01L29/66795
摘要： A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The gate dielectric region is sandwiched between the semiconductor region and the gate block. The semiconductor region is electrically insulated from the gate block by the gate dielectric region. The semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate. The semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate. Next, a gate region is formed from the gate block. Then, first and second source/drain regions are formed in the semiconductor region.
摘要翻译： 一种新颖的晶体管结构及其制造方法。 首先，提供衬底，半导体区域，栅极介质区域和栅极块。 半导体区域，栅极电介质区域和栅极块在衬底上。 栅极电介质区域夹在半导体区域和栅极块之间。 半导体区域通过栅极电介质区域与栅极块电绝缘。 半导体区域和栅极电介质区域共享基本上垂直于衬底顶表面的界面。 半导体区域和栅极介电区域不共享基本上平行于衬底顶表面的任何界面表面。 接下来，从栅极块形成栅极区域。 然后，在半导体区域中形成第一和第二源极/漏极区域。
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公开(公告)号：US07615454B2
公开(公告)日：2009-11-10
申请号：US11876415
申请日：2007-10-22
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/28247 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 Mpa.
摘要翻译： 本发明提供了一种半导体器件，其包括位于衬底的台面部分上的栅极区域; 以及位于所述栅极区域上的氮化物衬垫和与所述栅极区域相邻的所述衬底的凹陷表面，所述氮化物衬垫向所述栅极区域下方的器件沟道施加压力。 在器件通道上产生的应力是约275MPa至约450Mpa量级的纵向应力。
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10.发明授权公开(公告)号：US07476914B2
公开(公告)日：2009-01-13
申请号：US11555906
申请日：2006-11-02
申请人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
发明人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/0821 , H01L29/66242
摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.
摘要翻译： 提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。 所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。 富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。 然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。
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