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公开(公告)号：US11494107B2
公开(公告)日：2022-11-08
申请号：US16381969
申请日：2019-04-11
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan , Evgeny Televitckiy
Abstract: Disclosed herein are techniques for managing parity information for data stored on a storage device. A method includes (1) receiving a request to store data into the storage device, (2) storing portions of the data in data pages included in stripes in a band of the storage device, where a respective data page is stored on a respective different die of a respective stripe, (3) determining primary parity information for a first stripe including a subset of the data pages, (4) storing the primary parity information in a primary parity page included in a second stripe in the stripes in the band, where the primary parity page is disposed on a next available die relative to dies storing the data pages, (5) determining secondary parity information for the second stripe, and (6) storing the secondary parity information in a secondary parity page included in the stripes in the band.
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公开(公告)号：US11132145B2
公开(公告)日：2021-09-28
申请号：US16124154
申请日：2018-09-06
Applicant: Apple Inc.
Inventor： Yuhua Liu , Andrew W. Vogan , Matthew J. Byom , Alexander Paley
Abstract: Disclosed herein are techniques for reducing write amplification when processing write commands directed to a non-volatile memory. According to some embodiments, the method can include the steps of (1) receiving a first plurality of write commands and a second plurality of write commands, where the first plurality of write commands and the second plurality of write commands are separated by a fence command (2) caching the first plurality of write commands, the second plurality of write commands, and the fence command, and (3) in accordance with the fence command, and in response to identifying that at least one condition is satisfied: (i) issuing the first plurality of write commands to the non-volatile memory, (ii) issuing the second plurality of write commands to the non-volatile memory, and (iii) updating log information to reflect that the first plurality of write commands precede the second plurality of write commands.
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3.发明申请公开(公告)号：US20200379897A1
公开(公告)日：2020-12-03
申请号：US16425565
申请日：2019-05-29
Applicant: Apple Inc.
Inventor： Andrew W. Vogan
Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein define a native logical space to manage relatively high volume data write operations and define an artificially limited logical space to manage relatively low volume data write operations. The native logical space may include native logical bands that are mapped to a native number of physical blocks to enable high volume, high data transfer of data. The artificially limited logical space may include artificially limited logical bands that are mapped to an artificially limited number of available physical blocks. The artificially limited logical bands are better suited for low volume, low data transfer of data and do not unnecessarily tie up a native number of physical blocks.
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公开(公告)号：US09990023B2
公开(公告)日：2018-06-05
申请号：US15219984
申请日：2016-07-26
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan , Eran Sandel , Lior Mouler , Liran Erez , Matthew J. Byom , Muhammad N. Ashraf , Roman Guy
CPC classification number: G06F1/3275 , G06F1/263 , G06F1/30 , G06F1/3287 , G06F11/00
Abstract: Systems and methods for handling sudden power failures in non-volatile memory devices such as solid state drives are provided by having the non-volatile memory device boot up in a low power write mode, which limits substantially all programming operations to a single level cell (SLC) mode, as opposed to a normal mode in which the programming operations can be performed in a multi-level cell (MLC) mode. Thus, if the system experiences a sudden power failure when it is being powered solely by AC derived power and the battery is below a level sufficient for powering the device while it is programming in the SLC mode, data integrity will be preserved because the programming operation was being performed in SLC mode. The non-volatile memory device may be permitted to exit out the low power write mode into the normal mode when the charge level of the battery is sufficient for powering the system.
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公开(公告)号：US11972143B2
公开(公告)日：2024-04-30
申请号：US17222978
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Matthew J. Byom , Tudor Antoniu , Alexander Paley , Andrew W. Vogan , Muhammad N. Ashraf
IPC: G06F3/06 , G06F12/0875
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0644 , G06F3/0679 , G06F12/0875 , G06F2212/1016
Abstract: Disclosed herein are techniques for balancing write commands directed to a non-volatile memory. According to some embodiments, a method may include caching a plurality of write commands into a write cache, and, in response to determining that an available capacity of the write cache satisfies a first threshold value: performing at least one write operation by directing data associated with the write commands in the write cache to the first partition of the non-volatile memory in response to determining that an available capacity of a first partition of the non-volatile memory satisfies a second threshold value; and performing at least one write operation by directing data associated with the write commands in the write cache to a second partition of the non-volatile memory in response to determining that the available capacity of the first partition of the non-volatile memory does not satisfy the second threshold value.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10853199B2
公开(公告)日：2020-12-01
申请号：US16136189
申请日：2018-09-19
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan , Tudor Antoniu
Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.
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公开(公告)号：US09069695B2
公开(公告)日：2015-06-30
申请号：US13829088
申请日：2013-03-14
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Daniel J. Post
CPC classification number: G06F3/0619 , G06F3/0631 , G06F3/0679 , G06F11/1004 , G06F11/1008 , G06F11/1048
Abstract: Systems and methods are disclosed for correction block errors. In particular, a system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts.
Abstract translation: 公开了用于校正块错误的系统和方法。 特别地，系统可以每页模数地存储奇偶校验页，其中可以将NVM的块或带的预定数量的页分配为页模XOR（“PMX”）奇偶页。 这可以是用于从单块数据错误（例如，单页不可校正纠错码（“uECC”））和/或由字线短路引起的错误进行恢复的空间有效的方法。
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公开(公告)号：US12236119B2
公开(公告)日：2025-02-25
申请号：US17648540
申请日：2022-01-20
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan
IPC: G06F3/06
Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.
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9.发明授权公开(公告)号：US11544159B2
公开(公告)日：2023-01-03
申请号：US17033420
申请日：2020-09-25
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan , Tudor Antoniu
Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.
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公开(公告)号：US10379949B2
公开(公告)日：2019-08-13
申请号：US15721267
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Evgeny Televitckiy , Alexander Paley , Andrew W. Vogan
Abstract: Disclosed herein are techniques for managing parity information for data stored on a storage device. According to some embodiments, the method includes the steps of (1) receiving a request to store data into the storage device, (2) writing respective portions of the data into a plurality of data pages included in a first stripe of the storage device, where each data page is stored on a respective different die of the storage device, (3) calculating primary parity information for the first stripe, (4) writing the primary parity information into a primary parity page included in a second stripe of the storage device, (5) calculating secondary parity information for the second stripe, and (6) writing the secondary parity information into a secondary parity page included in a third stripe of the storage device. Additionally, a copy of the secondary parity information can be established to further-enhance redundancy.
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