公开(公告)号：US09189586B2

公开(公告)日：2015-11-17

申请号：US14217570

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract translation: 一种产生区域有效的功率开关单元的方法包括：由单元库设计工具接收要建立为单元库中的功率开关单元的功率开关电路的规格。 单元库设计工具还接收包括单元边界的高度的功率开关单元的一个或多个属性，并且由单元库设计工具接收布局布局约束，其要求将功率开关单元放置在半导体布局中，从而 桥接两排平行的掺杂阱。 掺杂阱的平行行与掺杂衬底交错，并且阱的掺杂与衬底的掺杂不同。 基于功率开关电路的规格，一个或多个属性和布局布局约束，单元库设计工具生成电源开关单元。

公开(公告)号：US20140380068A1

公开(公告)日：2014-12-25

申请号：US13921475

申请日：2013-06-19

Applicant: Apple Inc.

Inventor： Bo Tang ,  Ajay Kumar Bhatia

IPC: G06F1/32 ,  G05F1/46

CPC classification number: G06F1/3275 ,  G05F1/468 ,  G06F1/26 ,  G06F1/32

Abstract: A system including control logic, a voltage reference, a sense amplifier, and a voltage supply circuit is presented. The sense amplifier may be configured to detect a current state of the voltage supply circuit output compared to the reference voltage. The voltage supply circuit may be configured to capture and preserve the current state to be used as a previous state. The voltage regulator may be configured to compare the current state to one or more previous states and adjust the voltage regulator output based on the comparison. Control logic may be configured to enable the voltage reference output in response to a signal. Control logic may be configured to enable the sense amplifier at a time after the voltage reference is stable. Control logic may be configured to disable the voltage reference output in response to the sense amplifier generating an output.

Abstract translation: 提出了一种包括控制逻辑，电压基准，读出放大器和电压供应电路的系统。 读出放大器可被配置为检测与参考电压相比的电压供应电路输出的当前状态。 电压供给电路可以被配置为捕获并保持用作先前状态的当前状态。 电压调节器可以被配置为将当前状态与一个或多个先前状态进行比较，并且基于比较来调节稳压器输出。 控制逻辑可以被配置为响应于信号启用电压参考输出。 控制逻辑可以被配置为在电压参考稳定之后的时间使能读出放大器。 控制逻辑可以被配置为响应于感测放大器产生输出来禁用电压参考输出。

公开(公告)号：US09817937B2

公开(公告)日：2017-11-14

申请号：US14880420

申请日：2015-10-12

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

公开(公告)号：US20160034630A1

公开(公告)日：2016-02-04

申请号：US14880420

申请日：2015-10-12

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract translation: 一种产生区域有效的功率开关单元的方法包括：由单元库设计工具接收要建立为单元库中的功率开关单元的功率开关电路的规格。 单元库设计工具还接收包括单元边界的高度的功率开关单元的一个或多个属性，并且由单元库设计工具接收布局布局约束，其要求将功率开关单元放置在半导体布局中，从而 桥接两排平行的掺杂阱。 掺杂阱的平行行与掺杂衬底交错，并且阱的掺杂与衬底的掺杂不同。 基于功率开关电路的规格，一个或多个属性和布局布局约束，单元库设计工具生成电源开关单元。

公开(公告)号：US20140201698A1

公开(公告)日：2014-07-17

申请号：US14217570

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

公开(公告)号：US09698967B2

公开(公告)日：2017-07-04

申请号：US14851290

申请日：2015-09-11

Applicant: Apple Inc.

Inventor： Bo Tang ,  Abhijit D. Choudhury

IPC: H04L7/00 ,  G06F5/06 ,  G06F1/32 ,  G11C11/4076 ,  H04L12/863 ,  G11C7/22

CPC classification number: G06F5/06 ,  G06F1/324 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  H04L5/00 ,  H04L7/0008 ,  H04L7/0012 ,  H04L45/24 ,  H04L47/622

Abstract: A dual path source synchronous interface is disclosed. In one embodiment, a source synchronous interface includes a transmitter coupled to serially receive data from a first functional circuit block, and a receiver coupled to provide data serially to a second functional circuit block. Data is conveyed to the transmitter on a single signal line, and similarly, from the receiver on another single signal line. The transmitter is coupled to the receiver by two signal lines. The serial data received by the transmitter may be separated into two streams of alternating bits, e.g., a first bit is transmitted on one signal line, the next bit is transmitted on the other signal line, and so forth. At the receiver, the alternating bit streams may be re-combined into a single bit stream for transfer to the second functional circuit.

公开(公告)号：US20170078080A1

公开(公告)日：2017-03-16

申请号：US14851290

申请日：2015-09-11

Applicant: Apple Inc.

Inventor： Bo Tang ,  Abhijit D. Choudhury

IPC: H04L7/00 ,  H04L12/863 ,  G11C11/4076

CPC classification number: G06F5/06 ,  G06F1/324 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  H04L5/00 ,  H04L7/0008 ,  H04L7/0012 ,  H04L45/24 ,  H04L47/622

Abstract: A dual path source synchronous interface is disclosed. In one embodiment, a source synchronous interface includes a transmitter coupled to serially receive data from a first functional circuit block, and a receiver coupled to provide data serially to a second functional circuit block. Data is conveyed to the transmitter on a single signal line, and similarly, from the receiver on another single signal line. The transmitter is coupled to the receiver by two signal lines. The serial data received by the transmitter may be separated into two streams of alternating bits, e.g., a first bit is transmitted on one signal line, the next bit is transmitted on the other signal line, and so forth. At the receiver, the alternating bit streams may be re-combined into a single bit stream for transfer to the second functional circuit.

Abstract translation: 公开了一种双路径源同步接口。 在一个实施例中，源同步接口包括被耦合以串行地从第一功能电路块接收数据的发射器和被连接以提供数据到第二功能电路块的接收器。 在单个信号线上将数据传送到发射机，类似地，从另一个信号线上的接收机传送。 发射机通过两条信号线耦合到接收机。 由发射机接收的串行数据可以被分成两个交替比特流，例如，在一个信号线上发送第一比特，另一个信号线上发送下一个比特，等等。 在接收机处，交替的比特流可以被重新组合成单​​个比特流以传送到第二功能电路。

公开(公告)号：US09350326B2

公开(公告)日：2016-05-24

申请号：US14455195

申请日：2014-08-08

Applicant: Apple Inc.

Inventor： Bo Tang ,  Ajay Kumar Bhatia

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K5/24 ,  H03K5/249 ,  H03K19/0013

Abstract: A apparatus including a clock source and a comparison circuit is presented. The clock source may be configured to generate a clock signal. The comparison circuit may be configured select a first frequency of the clock signal and to receive a plurality of voltage signal inputs for comparison. The comparison circuit may be further configured to compare a voltage level of a first voltage signal input of the plurality of voltage signal inputs to a voltage level of a second voltage signal input of the plurality of voltage signal inputs responsive to an active edge of the clock signal. The comparison circuit may also be configured to determine a comparison value corresponding to the comparison of the voltage levels and to select a second frequency of the clock signal dependent upon the comparison value, in which the second frequency is different than the first frequency.

Abstract translation: 提出了一种包括时钟源和比较电路的装置。 时钟源可以被配置为产生时钟信号。 比较电路可以被配置为选择时钟信号的第一频率并且接收多个电压信号输入用于比较。 比较电路还可以被配置为将响应于时钟的有效边沿将多个电压信号输入的第一电压信号输入的电压电平与多个电压信号输入的第二电压信号输入的电压电平进行比较 信号。 比较电路还可以被配置为确定对应于电压电平的比较的比较值，并且根据比较值选择时钟信号的第二频率，其中第二频率不同于第一频率。

公开(公告)号：US08791743B1

公开(公告)日：2014-07-29

申请号：US13769406

申请日：2013-02-18

Applicant: Apple Inc.

Inventor： Bo Tang ,  Huaimin Li ,  Ajay Kumar Bhatia

IPC: H03L5/00

CPC classification number: H03K5/003 ,  H03K3/356104

Abstract: Embodiments of an apparatus are disclosed that may allow for the translation of signals from one power domain to another with well-balanced rise and fall times over a wide operational range. The apparatus may include an input buffer, a voltage shift circuit, and output circuit, and an output driver. The input buffer may be configured to generate a buffered version and delayed inverted version of an external signal at a first voltage level. The voltage shift circuit may be configured to generate two internal signals at a second voltage level dependent upon the output signals of the input buffer. The output circuit may be configured to generate two output driver signals at the second voltage level dependent upon the output signals of the voltage shift circuit. The output driver circuit may be configured to generate an output signal at the second voltage level dependent on the two output driver signals.

Abstract translation: 公开了一种装置的实施例，其可以允许将信号从一个功率域转换到另一个功率域，并且在宽的工作范围内具有良好平衡的上升和下降时间。 该装置可以包括输入缓冲器，电压移位电路和输出电路以及输出驱动器。 输入缓冲器可以被配置为在第一电压电平下产生缓冲版本和外部信号的延迟反相版本。 电压移位电路可以被配置为根据输入缓冲器的输出信号产生处于第二电压电平的两个内部信号。 输出电路可以被配置为根据电压移位电路的输出信号产生处于第二电压电平的两个输出驱动器信号。 输出驱动器电路可以被配置为根据两个输出驱动器信号产生处于第二电压电平的输出信号。

公开(公告)号：US20130067292A1

公开(公告)日：2013-03-14

申请号：US13672285

申请日：2012-11-08

Applicant: Apple Inc.

Inventor： Bo Tang ,  Edgardo F. Klass

IPC: G01R31/3177

CPC classification number: G01R31/318552 ,  G01R31/318594

Abstract: A number of scan flops clocked by a master clock may be used to constructing a scan chain to perform scan tests. During a scan test, data appearing at the regular data input of each scan flop may be written into a master latch of the scan flop during a time period when the scan control signal is in a state corresponding to a capture cycle. A slave latch in each scan flop may latch a value appearing at the regular data input of the scan flop according to a narrow pulse triggered by the rising edge of the master clock when the scan control signal is in the state corresponding to the capture cycle. The slave latch may latch the data provided by the master latch according to a wide pulse triggered by the rising edge of the master clock when the scan control signal is in a state corresponding to a shift cycle. This may permit toggling the scan control signal during either a high phase or a low phase of the master clock, and may also enable testing the pulse functionality of each scan flop.

Abstract translation: 可以使用由主时钟计时的多个扫描器来构建扫描链来执行扫描测试。 在扫描测试期间，在扫描控制信号处于与捕获周期对应的状态的时间段期间，出现在每个扫描触发器的常规数据输入端的数据可以写入扫描触发器的主锁存器。 当扫描控制信号处于与捕获周期对应的状态时，每个扫描触发器中的从锁存器可以根据由主时钟的上升沿触发的窄脉冲来锁存出现在扫描触发器的常规数据输入端的值。 当扫描控制信号处于与移位周期对应的状态时，从锁存器可以根据由主时钟的上升沿触发的宽脉冲来锁存由主锁存器提供的数据。 这可以允许在主时钟的高相位或低相位期间切换扫描控制信号，并且还可以使得能够测试每个扫描触发器的脉冲功能。